Interfacing AER devices to SpiNNaker using an FPGA

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This wiki page contains a collection of resources needed to interface AER sensors with SpiNNaker through a bidirectional inter-chip SpiNNaker link using an FPGA.


This application note describes the implementation of an interface between Address-Event Representation (AER) devices and the SpiNNaker system using an FPGA.

This document describes the cabling and protocol for AER boards.

verilog code

The example verilog code related to the application note can be found below:

  • spinn_aer2_if.tgz - Example Verilog code for bidirectional interface between SpiNNaker and AER devices using an FPGA
  • spinn_aer_if.v - Example Verilog file for interfacing AER sensors with SpiNNaker using an FPGA

Example setups

Interface with DVS - Instituto de Microelectronica, Universidad de Sevilla - using a RaggedStone2 FPGA board

Prototype interface with DVS - University of Osaka

Prototype Interface with the ATIS - Institut de La Vision, Paris