Uses of Enum Class
uk.ac.manchester.spinnaker.messages.model.FPGALinkRegisters
Packages that use FPGALinkRegisters
Package
Description
The BMP control subsystem.
Model support classes for the communication messages.
How to actually talk to a SpiNNaker machine.
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Uses of FPGALinkRegisters in uk.ac.manchester.spinnaker.alloc.bmp
Constructors in uk.ac.manchester.spinnaker.alloc.bmp with parameters of type FPGALinkRegistersModifierConstructorDescriptionRegisterSet
(FPGA fpga, FPGALinkRegisters register, int bank, int value) -
Uses of FPGALinkRegisters in uk.ac.manchester.spinnaker.messages.model
Methods in uk.ac.manchester.spinnaker.messages.model that return FPGALinkRegistersModifier and TypeMethodDescriptionstatic FPGALinkRegisters
Returns the enum constant of this class with the specified name.static FPGALinkRegisters[]
FPGALinkRegisters.values()
Returns an array containing the constants of this enum class, in the order they are declared. -
Uses of FPGALinkRegisters in uk.ac.manchester.spinnaker.transceiver
Methods in uk.ac.manchester.spinnaker.transceiver with parameters of type FPGALinkRegistersModifier and TypeMethodDescriptiondefault int
BMPTransceiverInterface.readFPGARegister
(FPGA fpga, int registerBank, FPGALinkRegisters register, @Valid BMPBoard board) Read a register on a FPGA of a board, assuming the standard FPGA configuration.default int
BMPTransceiverInterface.readFPGARegister
(FPGA fpga, int registerBank, FPGALinkRegisters register, @Valid BMPCoords bmp, @Valid BMPBoard board) Read a register on a FPGA of a board, assuming the standard FPGA configuration.default void
BMPTransceiverInterface.writeFPGARegister
(FPGA fpga, int registerBank, FPGALinkRegisters register, int value, @Valid BMPBoard board) Write a register on a FPGA of a board, assuming the standard FPGA configuration.default void
BMPTransceiverInterface.writeFPGARegister
(FPGA fpga, int registerBank, FPGALinkRegisters register, int value, @Valid BMPCoords bmp, @Valid BMPBoard board) Write a register on a FPGA of a board, assuming the standard FPGA configuration.