Package uk.ac.manchester.spinnaker.machine.datalinks

Enum Class FpgaEnum

java.lang.Object

java.lang.Enum<FpgaEnum>

uk.ac.manchester.spinnaker.machine.datalinks.FpgaEnum

All Implemented Interfaces:

Serializable, Comparable<FpgaEnum>, Constable, HasChipLocation

public enum FpgaEnum
extends Enum<FpgaEnum>
implements HasChipLocation

Hard codes all the supported FPGA Link IDs.

Based on the FPGA Diagram

Author:

Christian-B

Nested Class Summary

Nested classes/interfaces inherited from class java.lang.Enum

Enum.EnumDesc<E extends Enum<E>>

Enum Constant Summary

Enum Constants

Enum Constant	Description
FIVE_ONE_E	Link 4 on FPGA 0/Bottom From Chip(5,1) towards the East.
FIVE_ONE_S	Link 5 on FPGA 0/Bottom From Chip(5,1) towards the South.
FIVE_SEVEN_N	Link 2 on FPGA 2/TopRight From Chip(5,7) towards the North.
FIVE_SEVEN_NE	Link 3 on FPGA 2/TopRight From Chip(5,7) towards the NorthEast.
FOUR_SEVEN_N	Link 0 on FPGA 2/TopRight From Chip(4,7) towards the North.
FOUR_SEVEN_NE	Link 1 on FPGA 2/TopRight From Chip(4,7) towards the NorthEast.
FOUR_SEVEN_W	Link 15 on FPGA 1/Left From Chip(4,7) towards the West.
FOUR_ZERO_E	Link 6 on FPGA 0/Bottom From Chip(4,0) towards the East.
FOUR_ZERO_S	Link 7 on FPGA 0/Bottom From Chip(4,0) towards the South.
FOUR_ZERO_SW	Link 8 on FPGA 0/Bottom From Chip(4,0) towards the SouthWest.
ONE_FOUR_N	Link 10 on FPGA 1/Left From Chip(1,4) towards the North.
ONE_FOUR_W	Link 9 on FPGA 1/Left From Chip(1,4) towards the West.
ONE_ZERO_S	Link 13 on FPGA 0/Bottom From Chip(2,0) towards the South.
ONE_ZERO_SW	Link 14 on FPGA 0/Bottom From Chip(1,0) towards the SouthWest.
SEVEN_FIVE_E	Link 12 on FPGA 2/TopRight From Chip(7,5) towards the East.
SEVEN_FIVE_NE	Link 11 on FPGA 2/TopRight From Chip(7,5) towards the NorthEast.
SEVEN_FOUR_E	Link 14 on FPGA 2/TopRight From Chip(7,4) towards the East.
SEVEN_FOUR_NE	Link 13 on FPGA 2/TopRight From Chip(7,4) towards the NorthEast.
SEVEN_SEVEN_E	Link 8 on FPGA 2/TopRight From Chip(7,7) towards the East.
SEVEN_SEVEN_N	Link 6 on FPGA 2/TopRight From Chip(7,7) towards the North.
SEVEN_SEVEN_NE	Link 7 on FPGA 2/TopRight From Chip(7,7) towards the NorthEast.
SEVEN_SIX_E	Link 10 on FPGA 2/TopRight From Chip(7,6) towards the East.
SEVEN_SIX_NE	Link 9 on FPGA 2/TopRight From Chip(7,6) towards the NorthEast.
SEVEN_THREE_E	Link 0 on FPGA 0/Bottom From Chip(7,3) towards the East.
SEVEN_THREE_NE	Link 15 on FPGA 2/TopRight From Chip(7,3) towards the NorthEast.
SEVEN_THREE_S	Link 1 on FPGA 0/Bottom From Chip(7,3) towards the South.
SIX_SEVEN_N	Link 4 on FPGA 2/TopRight From Chip(6,7) towards the North.
SIX_SEVEN_NE	Link 5 on FPGA 2/TopRight From Chip(6,7) towards the NorthEast.
SIX_TWO_E	Link 2 on FPGA 0/Bottom From Chip(6,2) towards the East.
SIX_TWO_S	Link 3 on FPGA 0/Bottom From Chip(6,2) towards the South.
THREE_SIX_N	Link 14 on FPGA 1/Left From Chip(3,6) towards the North.
THREE_SIX_W	Link 13 on FPGA 1/Left From Chip(3,6) towards the West.
THREE_ZERO_S	Link 9 on FPGA 0/Bottom From Chip(3,0) towards the South.
THREE_ZERO_SW	Link 10 on FPGA 0/Bottom From Chip(3,0) towards the SouthWest.
TWO_FIVE_N	Link 12 on FPGA 1/Left From Chip(2,5) towards the North.
TWO_FIVE_W	Link 11 on FPGA 1/Left From Chip(2,5) towards the West.
TWO_ZERO_S	Link 11 on FPGA 0/Bottom From Chip(3,0) towards the South.
TWO_ZERO_SW	Link 12 on FPGA 0/Bottom From Chip(2,0) towards the SouthWest.
ZERO_ONE_SW	Link 2 on FPGA 1/Left From Chip(0,1) towards the SouthWest.
ZERO_ONE_W	Link 3 on FPGA 1/Left From Chip(0,1) towards the West.
ZERO_THREE_N	Link 8 on FPGA 1/Left From Chip(0,3) towards the North.
ZERO_THREE_SW	Link 6 on FPGA 1/Left From Chip(0,3) towards the SouthWest.
ZERO_THREE_W	Link 7 on FPGA 1/Left From Chip(0,3) towards the West.
ZERO_TWO_SW	Link 4 on FPGA 1/Left From Chip(0,2) towards the SouthWest.
ZERO_TWO_W	Link 5 on FPGA 1/Left From Chip(0,2) towards the West.
ZERO_ZERO_S	Link 15 on FPGA 0/Bottom From Chip(0,0) towards the South.
ZERO_ZERO_SW	Link 0 on FPGA 1/Left From Chip(0,0) towards the SouthWest.
ZERO_ZERO_W	Link 1 on FPGA 1/Left From Chip(0,0) towards the West.

Field Summary

Fields

Modifier and Type	Field	Description
final Direction	direction	Direction of the link as it comes out of the source Chip.
final FpgaId	fpgaId	ID of the FPGA.
final int	id	ID of the FPGA link.

Method Summary

Modifier and Type	Method	Description
ChipLocation	asChipLocation()	Converts (if required) this to a simple X, Y tuple.
static FpgaEnum	findId(int x, int y, Direction direction)	Find the enum by chip coordinates and the direction.
static FpgaEnum	findId(FpgaId fpgaId, int id)	Find the enum by FPGA and link IDs.
int	getX()
int	getY()
static FpgaEnum	valueOf(String name)	Returns the enum constant of this class with the specified name.
static FpgaEnum[]	values()	Returns an array containing the constants of this enum class, in the order they are declared.

Methods inherited from class java.lang.Enum

clone, compareTo, describeConstable, equals, finalize, getDeclaringClass, hashCode, name, ordinal, toString, valueOf

Methods inherited from class java.lang.Object

getClass, notify, notifyAll, wait, wait, wait

Methods inherited from interface uk.ac.manchester.spinnaker.machine.HasChipLocation

getScampCore, onSameChipAs

Enum Constant Details

ZERO_ZERO_SW

public static final FpgaEnum ZERO_ZERO_SW

Link 0 on FPGA 1/Left From Chip(0,0) towards the SouthWest.

ZERO_ZERO_W

public static final FpgaEnum ZERO_ZERO_W

Link 1 on FPGA 1/Left From Chip(0,0) towards the West.

ZERO_ONE_SW

public static final FpgaEnum ZERO_ONE_SW

Link 2 on FPGA 1/Left From Chip(0,1) towards the SouthWest.

ZERO_ONE_W

public static final FpgaEnum ZERO_ONE_W

Link 3 on FPGA 1/Left From Chip(0,1) towards the West.

ZERO_TWO_SW

public static final FpgaEnum ZERO_TWO_SW

Link 4 on FPGA 1/Left From Chip(0,2) towards the SouthWest.

ZERO_TWO_W

public static final FpgaEnum ZERO_TWO_W

Link 5 on FPGA 1/Left From Chip(0,2) towards the West.

ZERO_THREE_SW

public static final FpgaEnum ZERO_THREE_SW

Link 6 on FPGA 1/Left From Chip(0,3) towards the SouthWest.

ZERO_THREE_W

public static final FpgaEnum ZERO_THREE_W

Link 7 on FPGA 1/Left From Chip(0,3) towards the West.

ZERO_THREE_N

public static final FpgaEnum ZERO_THREE_N

Link 8 on FPGA 1/Left From Chip(0,3) towards the North.

ONE_FOUR_W

public static final FpgaEnum ONE_FOUR_W

Link 9 on FPGA 1/Left From Chip(1,4) towards the West.

ONE_FOUR_N

public static final FpgaEnum ONE_FOUR_N

Link 10 on FPGA 1/Left From Chip(1,4) towards the North.

TWO_FIVE_W

public static final FpgaEnum TWO_FIVE_W

Link 11 on FPGA 1/Left From Chip(2,5) towards the West.

TWO_FIVE_N

public static final FpgaEnum TWO_FIVE_N

Link 12 on FPGA 1/Left From Chip(2,5) towards the North.

THREE_SIX_W

public static final FpgaEnum THREE_SIX_W

Link 13 on FPGA 1/Left From Chip(3,6) towards the West.

THREE_SIX_N

public static final FpgaEnum THREE_SIX_N

Link 14 on FPGA 1/Left From Chip(3,6) towards the North.

FOUR_SEVEN_W

public static final FpgaEnum FOUR_SEVEN_W

Link 15 on FPGA 1/Left From Chip(4,7) towards the West.

FOUR_SEVEN_N

public static final FpgaEnum FOUR_SEVEN_N

Link 0 on FPGA 2/TopRight From Chip(4,7) towards the North.

FOUR_SEVEN_NE

public static final FpgaEnum FOUR_SEVEN_NE

Link 1 on FPGA 2/TopRight From Chip(4,7) towards the NorthEast.

FIVE_SEVEN_N

public static final FpgaEnum FIVE_SEVEN_N

Link 2 on FPGA 2/TopRight From Chip(5,7) towards the North.

FIVE_SEVEN_NE

public static final FpgaEnum FIVE_SEVEN_NE

Link 3 on FPGA 2/TopRight From Chip(5,7) towards the NorthEast.

SIX_SEVEN_N

public static final FpgaEnum SIX_SEVEN_N

Link 4 on FPGA 2/TopRight From Chip(6,7) towards the North.

SIX_SEVEN_NE

public static final FpgaEnum SIX_SEVEN_NE

Link 5 on FPGA 2/TopRight From Chip(6,7) towards the NorthEast.

SEVEN_SEVEN_N

public static final FpgaEnum SEVEN_SEVEN_N

Link 6 on FPGA 2/TopRight From Chip(7,7) towards the North.

SEVEN_SEVEN_NE

public static final FpgaEnum SEVEN_SEVEN_NE

Link 7 on FPGA 2/TopRight From Chip(7,7) towards the NorthEast.

SEVEN_SEVEN_E

public static final FpgaEnum SEVEN_SEVEN_E

Link 8 on FPGA 2/TopRight From Chip(7,7) towards the East.

SEVEN_SIX_NE

public static final FpgaEnum SEVEN_SIX_NE

Link 9 on FPGA 2/TopRight From Chip(7,6) towards the NorthEast.

SEVEN_SIX_E

public static final FpgaEnum SEVEN_SIX_E

Link 10 on FPGA 2/TopRight From Chip(7,6) towards the East.

SEVEN_FIVE_NE

public static final FpgaEnum SEVEN_FIVE_NE

Link 11 on FPGA 2/TopRight From Chip(7,5) towards the NorthEast.

SEVEN_FIVE_E

public static final FpgaEnum SEVEN_FIVE_E

Link 12 on FPGA 2/TopRight From Chip(7,5) towards the East.

SEVEN_FOUR_NE

public static final FpgaEnum SEVEN_FOUR_NE

Link 13 on FPGA 2/TopRight From Chip(7,4) towards the NorthEast.

SEVEN_FOUR_E

public static final FpgaEnum SEVEN_FOUR_E

Link 14 on FPGA 2/TopRight From Chip(7,4) towards the East.

SEVEN_THREE_NE

public static final FpgaEnum SEVEN_THREE_NE

Link 15 on FPGA 2/TopRight From Chip(7,3) towards the NorthEast.

SEVEN_THREE_E

public static final FpgaEnum SEVEN_THREE_E

Link 0 on FPGA 0/Bottom From Chip(7,3) towards the East.

SEVEN_THREE_S

public static final FpgaEnum SEVEN_THREE_S

Link 1 on FPGA 0/Bottom From Chip(7,3) towards the South.

SIX_TWO_E

public static final FpgaEnum SIX_TWO_E

Link 2 on FPGA 0/Bottom From Chip(6,2) towards the East.

SIX_TWO_S

public static final FpgaEnum SIX_TWO_S

Link 3 on FPGA 0/Bottom From Chip(6,2) towards the South.

FIVE_ONE_E

public static final FpgaEnum FIVE_ONE_E

Link 4 on FPGA 0/Bottom From Chip(5,1) towards the East.

FIVE_ONE_S

public static final FpgaEnum FIVE_ONE_S

Link 5 on FPGA 0/Bottom From Chip(5,1) towards the South.

FOUR_ZERO_E

public static final FpgaEnum FOUR_ZERO_E

Link 6 on FPGA 0/Bottom From Chip(4,0) towards the East.

FOUR_ZERO_S

public static final FpgaEnum FOUR_ZERO_S

Link 7 on FPGA 0/Bottom From Chip(4,0) towards the South.

FOUR_ZERO_SW

public static final FpgaEnum FOUR_ZERO_SW

Link 8 on FPGA 0/Bottom From Chip(4,0) towards the SouthWest.

THREE_ZERO_S

public static final FpgaEnum THREE_ZERO_S

Link 9 on FPGA 0/Bottom From Chip(3,0) towards the South.

THREE_ZERO_SW

public static final FpgaEnum THREE_ZERO_SW

Link 10 on FPGA 0/Bottom From Chip(3,0) towards the SouthWest.

TWO_ZERO_S

public static final FpgaEnum TWO_ZERO_S

Link 11 on FPGA 0/Bottom From Chip(3,0) towards the South.

TWO_ZERO_SW

public static final FpgaEnum TWO_ZERO_SW

Link 12 on FPGA 0/Bottom From Chip(2,0) towards the SouthWest.

ONE_ZERO_S

public static final FpgaEnum ONE_ZERO_S

Link 13 on FPGA 0/Bottom From Chip(2,0) towards the South.

ONE_ZERO_SW

public static final FpgaEnum ONE_ZERO_SW

Link 14 on FPGA 0/Bottom From Chip(1,0) towards the SouthWest.

ZERO_ZERO_S

public static final FpgaEnum ZERO_ZERO_S

Link 15 on FPGA 0/Bottom From Chip(0,0) towards the South.

Field Details

direction

public final Direction direction

Direction of the link as it comes out of the source Chip.

fpgaId

public final FpgaId fpgaId

ID of the FPGA.

id

public final int id

ID of the FPGA link.

Method Details

values

public static FpgaEnum[] values()

Returns an array containing the constants of this enum class, in the order they are declared.

Returns:

an array containing the constants of this enum class, in the order they are declared

valueOf

public static FpgaEnum valueOf(String name)

Returns the enum constant of this class with the specified name. The string must match exactly an identifier used to declare an enum constant in this class. (Extraneous whitespace characters are not permitted.)

Parameters:

name - the name of the enum constant to be returned.

Returns:

the enum constant with the specified name

Throws:

IllegalArgumentException - if this enum class has no constant with the specified name

NullPointerException - if the argument is null

getX

public int getX()

Specified by:

getX in interface HasChipLocation

Returns:

The X coordinate of the chip.

getY

public int getY()

Specified by:

getY in interface HasChipLocation

Returns:

The Y coordinate of the chip.

asChipLocation

public ChipLocation asChipLocation()

Description copied from interface: HasChipLocation

Converts (if required) this to a simple X, Y tuple.

Specified by:

asChipLocation in interface HasChipLocation

Returns:

A ChipLocation representation of the X and Y tuple

findId

public static FpgaEnum findId(int x,
 int y,
 Direction direction)

Find the enum by chip coordinates and the direction.

Parameters:

x - X coordinate of chip.

y - X coordinate of chip.

direction - Direction of the link covered by the FPGA.

Returns:

The corresponding enum value.

Throws:

IllegalArgumentException - If the arguments don't describe a supported FPGA link.

findId

public static FpgaEnum findId(FpgaId fpgaId,
 int id)

Find the enum by FPGA and link IDs.

Parameters:

fpgaId - ID of the FPGA device.

id - ID of the link on that device.

Returns:

The corresponding enum value.

Throws:

IllegalArgumentException - If the arguments don't describe a supported FPGA link.