Extra definitions of things on SpiNNaker chips that aren't already mentioned in spinnaker.h, or where the description is miserable. More...

#include <spinnaker.h>
#include <stdbool.h>

Data Structures
union	vic_mask_t
	Mask describing interrupts that can be selected. More...

struct	vic_mask_t::interrupt_bits
	See datasheet section 5.4 Interrupt sources More...

struct	vic_control_t
	VIC registers. More...

struct	vic_vector_control_t
	VIC individual vector control. More...

struct	timer_control_t
	Timer control register. More...

struct	timer_interrupt_status_t
	Timer interrupt status flag. More...

struct	timer_controller_t
	Timer controller registers. More...

struct	dma_description_t
	DMA descriptor. More...

struct	dma_control_t
	DMA control register. More...

struct	dma_status_t
	DMA status register. More...

struct	dma_global_control_t
	DMA global control register. More...

struct	dma_timeout_t
	DMA timeout register. More...

struct	dma_stats_control_t
	DMA statistics control register. More...

struct	dma_t
	DMA controller registers. More...

union	spinnaker_packet_control_byte_t
	The control byte of a SpiNNaker packet. More...

struct	spinnaker_packet_control_byte_t::common
	Common fields. More...

struct	spinnaker_packet_control_byte_t::mc
	Multicast packet only fields. More...

struct	spinnaker_packet_control_byte_t::p2p
	Peer-to-peer packet only fields. More...

struct	spinnaker_packet_control_byte_t::nn
	Nearest-neighbour packet only fields. More...

struct	spinnaker_packet_control_byte_t::fr
	Fixed-route packet only fields. More...

struct	comms_tx_control_t
	Controls packet transmission. More...

struct	comms_rx_status_t
	Indicates packet reception status. More...

struct	comms_source_addr_t
	P2P source address. More...

struct	comms_ctl_t
	SpiNNaker communications controller registers. More...

struct	router_control_t
	Router control register. More...

struct	router_status_t
	Router status. More...

union	router_packet_header_t
	Router error/dump header. More...

struct	router_packet_header_t::flags
	Fields in router_packet_header_t. More...

struct	router_packet_header_t::control_field_bits
	Critical fields in router_packet_header_t::flags::control. More...

struct	router_error_status_t
	Router error status. More...

struct	router_dump_outputs_t
	Router dump outputs. More...

struct	router_dump_status_t
	Router dump status. More...

struct	router_diagnostic_counter_ctrl_t
	Router diagnostic counter enable/reset. More...

struct	router_timing_counter_ctrl_t
	Router timing counter controls. More...

struct	router_diversion_t
	Router diversion rules, used to handle default-routed packets. More...

struct	router_fixed_route_routing_t
	Fixed route and nearest neighbour packet routing control. More...

struct	router_t
	SpiNNaker router controller registers. More...

struct	router_t::error
	Error-related registers. More...

struct	router_t::dump
	Packet-dump-related registers. More...

struct	router_diagnostic_filter_t
	SpiNNaker router diagnostic filter. More...

union	router_multicast_route_t
	SpiNNaker router multicast route. More...

struct	router_multicast_route_t::routes
	Where to route a matching entry to. More...

union	router_p2p_table_entry_t
	A packed word in the P2P routing table. More...

struct	router_p2p_table_entry_t::routes
	The eight individual routes making up a P2P table entry. More...

struct	sdram_status_t
	Memory controller status. More...

struct	sdram_command_t
	Memory controller command. More...

struct	sdram_direct_command_t
	Memory controller direct command. More...

struct	sdram_ram_config_t
	Memory configuration. More...

struct	sdram_refresh_t
	Memory refresh period. More...

struct	sdram_cas_latency_t
	Memory CAS latency. More...

struct	sdram_timing_config_t
	Memory timimg configuration. More...

struct	sdram_controller_t
	Memory controller registers. More...

struct	sdram_qos_t
	Memory QoS settings. More...

struct	sdram_chip_t
	Memory chip configuration. More...

struct	sdram_dll_status_t
	Memory delay-locked-loop (DLL) test and status inputs. More...

struct	sdram_dll_user_config0_t
	Memory delay-locked-loop (DLL) test and control outputs. More...

union	sdram_dll_user_config1_t
	Memory delay-locked-loop (DLL) fine-tune control. More...

struct	sdram_dll_user_config1_t::tuning
	Tuning fields. More...

struct	sdram_dll_t
	SDRAM delay-locked-loop (DLL) control registers. More...

struct	sc_magic_proc_map_t
	System controller processor select. More...

struct	sc_magic_subsystem_map_t
	System controller subsystem reset target select. More...

struct	sc_reset_code_t
	System controller last reset status. More...

struct	sc_monitor_id_t
	System controller monitor election control. More...

struct	sc_misc_control_t
	System controller miscellaneous control. More...

union	sc_io_t
	System controller general chip I/O pin access. More...

struct	sc_io_t::io_bits
	Control over I/O pins used for non-GPIO purposes. More...

struct	sc_pll_control_t
	System controller phase-locked-loop control. More...

struct	sc_clock_mux_t
	System controller clock multiplexing control. More...

struct	sc_sleep_status_t
	System controller sleep status. More...

struct	sc_temperature_t
	System controller temperature status/control. More...

struct	sc_mutex_bit_t
	System controller mutex/interlock. More...

struct	sc_link_disable_t
	System controller link and router control. More...

struct	system_controller_t
	System controller registers. More...

struct	ethernet_general_command_t
	Ethernet general command. More...

struct	ethernet_general_status_t
	Ethernet general status. More...

struct	ethernet_tx_length_t
	Ethernet frame transmit length. More...

struct	ethernet_phy_control_t
	Ethernet PHY (physical layer) control. More...

struct	ethernet_interrupt_clear_t
	Ethernet interrupt clear register. More...

struct	ethernet_receive_pointer_t
	Ethernet receive data pointer. More...

struct	ethernet_receive_descriptor_pointer_t
	Ethernet receive descriptor pointer. More...

struct	ethernet_controller_t
	Ethernet controller registers. More...

struct	ethernet_receive_descriptor_t
	Ethernet received message descriptor. More...

struct	watchdog_control_t
	Watchdog timer control register. More...

struct	watchdog_status_t
	Watchdog timer status registers. More...

union	watchdog_lock_t
	Watchdog timer lock register. More...

struct	watchdog_lock_t::fields
	The fields in the lock register. More...

struct	watchdog_controller_t
	Watchdog timer control registers. More...

Macros
#define	ASSERT_WORD_SIZED(type_ident)
	Generates valid code if the named type is one word long, and invalid code otherwise.

6. Counter/Timer
Every core has a pair of counters/timers. The counter/timers use the standard AMBA peripheral device described on page 4-24 of the AMBA Design Kit Technical Reference Manual ARM DDI 0243A, February 2003. The peripheral has been modified only in that the APB interface of the original has been replaced by an AHB interface for direct connection to the ARM968 AHB bus.
enum	timer_pre_divide { TIMER_PRE_DIVIDE_1 = 0 , TIMER_PRE_DIVIDE_16 = 1 , TIMER_PRE_DIVIDE_256 = 2 }
	Values for timer_control_t::pre_divide. More...

static volatile timer_controller_t *const	timer1_control
	Timer 1 control registers.

static volatile timer_controller_t *const	timer2_control
	Timer 2 control registers.

7. DMA Controller
Each ARM968 processing subsystem includes a DMA controller. The DMA controller is primarily used for transferring inter-neural connection data from the SDRAM in large blocks in response to an input event arriving at a fascicle processor, and for returning updated connection data during learning. In addition, the DMA controller can transfer data to/from other targets on the System NoC such as the System RAM and Boot ROM. As a secondary function the DMA controller incorporates a ‘Bridge’ across which its host ARM968 has direct read and write access to System NoC devices, including the SDRAM. The ARM968 can use the Bridge whether or not DMA transfers are active.
enum	dma_direction_t { DMA_DIRECTION_READ , DMA_DIRECTION_WRITE }
	DMA transfer direction, see dma_description_t::direction. More...

enum	dma_transfer_unit_t { DMA_TRANSFER_WORD , DMA_TRANSFER_DOUBLE_WORD }
	DMA burst width, see dma_description_t::width. More...

static volatile dma_t *const	dma_control = (dma_t *) DMA_BASE
	DMA control registers.

8. Communications controller
Each processor node on SpiNNaker includes a communications controller which is responsible for generating and receiving packets to and from the communications network.
enum	spinnaker_packet_type_t { SPINNAKER_PACKET_TYPE_MC = 0 , SPINNAKER_PACKET_TYPE_P2P = 1 , SPINNAKER_PACKET_TYPE_NN = 2 , SPINNAKER_PACKET_TYPE_FR = 3 }
	SpiNNaker packet type codes. More...

static volatile comms_ctl_t *const	comms_control = (comms_ctl_t *) CC_BASE
	Communications controller registers.

10. SpiNNaker Router
The Router is responsible for routing all packets that arrive at its input to one or more of its outputs. It is responsible for routing multicast neural event packets, which it does through an associative multicast router subsystem, point-to-point packets (for which it uses a look-up table), nearest-neighbour packets (using a simple algorithmic process), fixed-route packet routing (defined in a register), default routing (when a multicast packet does not match any entry in the multicast router) and emergency routing (when an output link is blocked due to congestion or hardware failure). Various error conditions are identified and handled by the Router, for example packet parity errors, time-out, and output link failure.
enum	router_output_stage { ROUTER_OUTPUT_STAGE_EMPTY , ROUTER_OUTPUT_STAGE_FULL , ROUTER_OUTPUT_STAGE_WAIT1 , ROUTER_OUTPUT_STAGE_WAIT2 }
	Stages in router_status_t::output_stage. More...

enum	router_diversion_rule_t { ROUTER_DIVERSION_NORMAL , ROUTER_DIVERSION_MONITOR , ROUTER_DIVERSION_DESTROY }
	Diversion rules for the fields of router_diversion_t. More...

enum	router_p2p_route { ROUTER_P2P_ROUTE_E , ROUTER_P2P_ROUTE_NE , ROUTER_P2P_ROUTE_N , ROUTER_P2P_ROUTE_W , ROUTER_P2P_ROUTE_SW , ROUTER_P2P_ROUTE_S , ROUTER_P2P_ROUTE_DROP , ROUTER_P2P_ROUTE_MONITOR }
	The possible values of a P2P route. More...

static volatile router_t *const	router_control = (router_t *) RTR_BASE
	Router controller registers.

static volatile router_diagnostic_filter_t *const	router_diagnostic_filter
	Router diagnostic filters.

static volatile uint *const	router_diagnostic_counter
	Router diagnostic counters.

static volatile router_multicast_route_t *const	router_multicast_table
	Router multicast route table.

static volatile uint *const	router_key_table = (uint *) RTR_MCKEY_BASE
	Router multicast key table (write only!)

static volatile uint *const	router_mask_table = (uint *) RTR_MCMASK_BASE
	Router multicast mask table (write only!)

static volatile router_p2p_table_entry_t *const	router_p2p_route_table
	Router peer-to-peer route table.

13. SDRAM interface
The SDRAM interface connects the System NoC to an off-chip SDRAM device. It is the ARM PL340, described in ARM document DDI 0331D. Only meaningfully usable by the monitor core when initialising the overall chip. Use at other times is very much not recommended. Warning Do not use these without talking to Luis first!
enum	sdram_command { SDRAM_CTL_GO , SDRAM_CTL_SLEEP , SDRAM_CTL_WAKE , SDRAM_CTL_PAUSE , SDRAM_CTL_CONFIG , SDRAM_CTL_ACTIVE_PAUSE }
	Memory controller commands, for sdram_command_t::command. More...

enum	sdram_direct_command { SDRAM_DIRECT_PRECHARGE = 0 , SDRAM_DIRECT_AUTOREFRESH = 1 , SDRAM_DIRECT_MODEREG = 2 , SDRAM_DIRECT_NOP = 3 }
	Memory direct commands, for sdram_direct_command_t::cmd. More...

enum	sdram_register_maxima { SDRAM_QOS_MAX = 15 , SDRAM_CHIP_MAX = 3 }
	Maximum register IDs. More...

static volatile sdram_controller_t *const	sdram_control
	SDRAM interface control registers.

static volatile sdram_qos_t *const	sdram_qos_control
	SDRAM QoS control registers.

static volatile sdram_chip_t *const	sdram_chip_control
	SDRAM chip control registers.

static volatile sdram_dll_t *const	sdram_dll_control
	SDRAM delay-locked-loop control registers.

14. System Controller
The System Controller incorporates a number of functions for system start-up, fault-tolerance testing (invoking, detecting and resetting faults), general performance monitoring, etc. Features: 'Arbiter' read-sensitive register bit to determine Monitor Processor ID at start-up. 32 test-and-set registers for general software use, e.g. to enforce mutually exclusive access to critical data structures. individual interrupt, reset and enable controls and 'processor OK' status bits for each processor. sundry parallel IO and test and control registers. PLL and clock management registers. Note All processor IDs should be physical processor IDs.
enum	sc_reset_codes { SC_RESET_CODE_POR , SC_RESET_CODE_WDR , SC_RESET_CODE_UR , SC_RESET_CODE_REC , SC_RESET_CODE_WDI }
	System controller chip reset reasons. More...

enum	sc_frequency_range { FREQ_25_50 , FREQ_50_100 , FREQ_100_200 , FREQ_200_400 }
	Frequency range constants for sc_pll_control_t::freq_range. More...

enum	sc_clock_source { CLOCK_SRC_EXT , CLOCK_SRC_PLL1 , CLOCK_SRC_PLL2 , CLOCK_SRC_EXT4 }
	System controller clock sources. More...

enum	sc_magic { SYSTEM_CONTROLLER_MAGIC_NUMBER = 0x5ec }
	System controller magic numbers. More...

static volatile system_controller_t *const	system_control
	System controller registers.

15. Ethernet Media-independent interface (MII)
The SpiNNaker system connects to a host machine via Ethernet links. Each SpiNNaker chip includes an Ethernet MII interface, although only a few of the chips are expected to use this interface. These chips will require an external PHY. Note The implementation does not provide support for half-duplex operation (as required by a CSMA/CD MAC algorithm), jumbo or VLAN frames.
enum	ethernet_tx_length_limits { ETHERNET_TX_LENGTH_MIN = 60 , ETHERNET_TX_LENGTH_MAX = 1514 }
	Limits of ethernet_tx_length_t::tx_length. More...

static volatile uchar *const	ethernet_tx_buffer = (uchar *) ETH_TX_BASE
	Ethernet transmit buffer.

static volatile uchar *const	ethernet_rx_buffer = (uchar *) ETH_RX_BASE
	Ethernet receive buffer.

static volatile ethernet_receive_descriptor_t *const	ethernet_desc_buffer
	Ethernet receive descriptor buffer.

static volatile ethernet_controller_t *const	ethernet_control
	Ethernet MII controller registers.

16. Watchdog timer
The watchdog timer is an ARM PrimeCell component (ARM part SP805, documented in ARM DDI 0270B) that is responsible for applying a system reset when a failure condition is detected. Normally, the Monitor Processor will be responsible for resetting the watchdog periodically to indicate that all is well. If the Monitor Processor should crash, or fail to reset the watchdog during a pre-determined period of time, the watchdog will trigger.
enum	watchdog_lock_codes { WATCHDOG_LOCK_RESET = 0 , WATCHDOG_LOCK_MAGIC = WD_CODE }
	Watchdog timer lock codes, for watchdog_lock_t::whole_value. More...

static volatile watchdog_controller_t *const	watchdog_control
	Watchdog timer controller registers.

5. Vectored Interrupt Controller
The VIC is used to enable and disable interrupts from various sources, and to wake the processor from sleep mode when required. Each processor node on an SpiNNaker chip has a vectored interrupt controller (VIC) that is used to enable and disable interrupts from various sources, and to wake the processor from sleep mode when required. The interrupt controller provides centralised management of IRQ and FIQ sources, and offers an efficient indication of the active sources for IRQ vectoring purposes. The VIC is the ARM PL190, described in ARM DDI 0181E.
typedef void(*	vic_interrupt_handler_t) (void)
	The type of an interrupt handler.

static volatile vic_control_t *const	vic_control
	VIC registers.

static volatile vic_interrupt_handler_t *const	vic_interrupt_vector
	VIC interrupt handlers. Array of 32 elements.

static volatile vic_vector_control_t *const	vic_interrupt_control
	VIC individual interrupt control. Array of 32 elements.

Detailed Description

Extra definitions of things on SpiNNaker chips that aren't already mentioned in spinnaker.h, or where the description is miserable.

This models data structures described in the SpiNNaker datasheet. Before using anything in this file, you should read the relevant section of the datasheet so as you can understand the correct usage patterns for the underlying hardware.

Definition in file spinn_extra.h.

Data Structure Documentation

◆ vic_mask_t

union vic_mask_t

Mask describing interrupts that can be selected.

Definition at line 105 of file spinn_extra.h.

Data Fields
uint	value	Whole mask as integer.

◆ vic_mask_t::interrupt_bits

struct vic_mask_t::interrupt_bits

See datasheet section 5.4 Interrupt sources

Definition at line 107 of file spinn_extra.h.

Data Fields
uint	watchdog: 1	Watchdog timer interrupt.
uint	software: 1	Local software interrupt generation.
uint	comm_rx: 1	Debug communications receiver interrupt.
uint	comm_tx: 1	Debug communications transmitter interrupt.
uint	timer1: 1	Counter/timer interrupt 1.
uint	timer2: 1	Counter/timer interrupt 2.
uint	cc_rx_ready: 1	Comms controller packet received.
uint	cc_rx_parity_error: 1	Comms controller received packet parity error.
uint	cc_rx_framing_error: 1	Comms controller received packet framing error.
uint	cc_tx_full: 1	Comms controller transmit buffer full.
uint	cc_tx_overflow: 1	Comms controller transmit buffer overflow.
uint	cc_tx_empty: 1	Comms controller transmit buffer empty.
uint	dma_done: 1	DMA controller transfer complete.
uint	dma_error: 1	DMA controller error.
uint	dma_timeout: 1	DMA controller transfer timed out.
uint	router_diagnostic: 1	Router diagnostic counter event has occurred.
uint	router_dump: 1	Router packet dumped - indicates failed delivery.
uint	router_error: 1	Router error - packet parity, framing, or time stamp error.
uint	cpu: 1	System Controller interrupt bit set for this processor.
uint	ethernet_tx: 1	Ethernet transmit frame interrupt.
uint	ethernet_rx: 1	Ethernet receive frame interrupt.
uint	ethernet_phy: 1	Ethernet PHY/external interrupt.
uint	slow_clock: 1	System-wide slow (nominally 32 KHz) timer interrupt.
uint	cc_tx_not_full: 1	Comms controller can accept new Tx packet.
uint	cc_rx_mc: 1	Comms controller multicast packet received.
uint	cc_rx_p2p: 1	Comms controller point-to-point packet received.
uint	cc_rx_nn: 1	Comms controller nearest neighbour packet received.
uint	cc_rx_fr: 1	Comms controller fixed route packet received.
uint	int0: 1	External interrupt request 0.
uint	int1: 1	External interrupt request 1.
uint	gpio8: 1	Signal on GPIO[8].
uint	gpio9: 1	Signal on GPIO[9].

◆ vic_control_t

struct vic_control_t

VIC registers.

Definition at line 178 of file spinn_extra.h.

Data Fields
const vic_mask_t	irq_status	IRQ status register.
const vic_mask_t	fiq_status	FIQ status register.
const vic_mask_t	raw_status	raw interrupt status register
vic_mask_t	int_select	interrupt select register
vic_mask_t	int_enable	interrupt enable set register
vic_mask_t	int_disable	interrupt enable clear register
vic_mask_t	soft_int_enable	soft interrupt set register
vic_mask_t	soft_int_disable	soft interrupt clear register
bool	protection	protection register
vic_interrupt_handler_t	vector_address	current vector address register
vic_interrupt_handler_t	default_vector_address	default vector address register

◆ vic_vector_control_t

struct vic_vector_control_t

VIC individual vector control.

Definition at line 206 of file spinn_extra.h.

Data Fields
uint	source: 5	interrupt source
uint	enable: 1	interrupt enable

◆ timer_control_t

struct timer_control_t

Timer control register.

Definition at line 244 of file spinn_extra.h.

Data Fields
uint	one_shot: 1	0 = wrapping mode, 1 = one shot
uint	size: 1	0 = 16 bit, 1 = 32 bit
uint	pre_divide: 2	divide input clock (see timer_pre_divide)
uint	interrupt_enable: 1	enable interrupt (1 = enabled)
uint	periodic_mode: 1	0 = free-running; 1 = periodic
uint	enable: 1	enable counter/timer (1 = enabled)

◆ timer_interrupt_status_t

struct timer_interrupt_status_t

Timer interrupt status flag.

Definition at line 274 of file spinn_extra.h.

Data Fields
uint	status: 1	The flag bit.

◆ timer_controller_t

struct timer_controller_t

Timer controller registers.

Definition at line 282 of file spinn_extra.h.

Data Fields
uint	load_value	Load value for Timer.
const uint	current_value	Current value of Timer.
timer_control_t	control	Timer control register.
uint	interrupt_clear	Interrupt clear (any value may be written)
const timer_interrupt_status_t	raw_interrupt_status	Timer raw interrupt status.
const timer_interrupt_status_t	masked_interrupt_status	Timer masked interrupt status.
uint	background_load_value	Background load value for Timer.

◆ dma_description_t

struct dma_description_t

DMA descriptor.

Definition at line 330 of file spinn_extra.h.

Data Fields
uint	length_words: 15	length of the DMA transfer, in words
uint	direction: 1	read from or write to system bus, see dma_direction_t
uint	crc: 1	check (read) or generate (write) CRC
uint	burst: 3	burst length = 2^B×Width, B = 0..4 (i.e max 16)
uint	width: 1	transfer width, see dma_transfer_unit_t
uint	privilege: 1	DMA transfer mode is user (0) or privileged (1)
uint	transfer_id: 6	software defined transfer ID

◆ dma_control_t

struct dma_control_t

DMA control register.

Definition at line 368 of file spinn_extra.h.

Data Fields
uint	uncommit: 1	setting this bit uncommits a queued transfer
uint	abort: 1	end current transfer and discard data
uint	restart: 1	resume transfer (clears DMA errors)
uint	clear_done_int: 1	clear Done interrupt request
uint	clear_timeout_int: 1	clear Timeout interrupt request
uint	clear_write_buffer_int: 1	clear Write Buffer interrupt request

◆ dma_status_t

struct dma_status_t

DMA status register.

Definition at line 386 of file spinn_extra.h.

Data Fields
uint	transferring: 1	DMA transfer in progress.
uint	paused: 1	DMA transfer is PAUSED.
uint	queued: 1	DMA transfer is queued - registers are full.
uint	write_buffer_full: 1	write buffer is full
uint	write_buffer_active: 1	write buffer is not empty
uint	transfer_done: 1	a DMA transfer has completed without error
uint	transfer2_done: 1	2nd DMA transfer has completed without error
uint	timeout: 1	a burst transfer has not completed in time
uint	crc_error: 1	the calculated and received CRCs differ
uint	tcm_error: 1	the TCM AHB interface has signalled an error
uint	axi_error: 1	the AXI interface (SDRAM) has signalled a transfer error
uint	user_abort: 1	the user has aborted the transfer (via dma_control_t::abort)
uint	soft_reset: 1	a soft reset of the DMA controller has happened
uint	write_buffer_error: 1	a buffered write transfer has failed
uint	processor_id: 8	hardwired processor ID identifies CPU on chip

◆ dma_global_control_t

struct dma_global_control_t

DMA global control register.

Definition at line 426 of file spinn_extra.h.

Data Fields
uint	bridge_buffer_enable: 1	enable Bridge write buffer
uint	transfer_done_interrupt: 1	interrupt if dma_status_t::transfer_done set
uint	transfer2_done_interrupt: 1	interrupt if dma_status_t::transfer2_done set
uint	timeout_interrupt: 1	interrupt if dma_status_t::timeout set
uint	crc_error_interrupt: 1	interrupt if dma_status_t::crc_error set
uint	tcm_error_interrupt: 1	interrupt if dma_status_t::tcm_error set
uint	axi_error_interrupt: 1	interrupt if dma_status_t::axi_error set
uint	user_abort_interrupt: 1	interrupt if dma_status_t::user_abort set
uint	soft_reset_interrupt: 1	interrupt if dma_status_t::soft_reset set
uint	write_buffer_error_interrupt: 1	interrupt if dma_status_t::write_buffer_error set
uint	timer: 1	system-wide slow timer status and clear

◆ dma_timeout_t

struct dma_timeout_t

DMA timeout register.

Definition at line 458 of file spinn_extra.h.

Data Fields
uint	value: 5	The timeout.

◆ dma_stats_control_t

struct dma_stats_control_t

DMA statistics control register.

Definition at line 468 of file spinn_extra.h.

Data Fields
uint	enable: 1	Enable collecting DMA statistics.
uint	clear: 1	Clear the statistics registers (if 1)

◆ dma_t

struct dma_t

DMA controller registers.

Definition at line 478 of file spinn_extra.h.

Data Fields
void *	sdram_address	DMA address on the system interface.
void *	tcm_address	DMA address on the TCM interface.
dma_description_t	description	DMA transfer descriptor; note that setting this commits a DMA.
dma_control_t	control	Control DMA transfer.
const dma_status_t	status	Status of DMA and other transfers.
dma_global_control_t	global_control	Control of the DMA device.
const uint	crcc	CRC value calculated by CRC block.
const uint	crcr	CRC value in received block.
dma_timeout_t	timeout	Timeout value.
dma_stats_control_t	statistics_control	Statistics counters control.
const uint	statistics[8]	Statistics counters.
const void *	current_sdram_address	Active system address.
const void *	current_tcm_address	Active TCM address.
const dma_description_t	current_description	Active transfer description.
uint	crc_polynomial[32]	CRC polynomial matrix.

◆ spinnaker_packet_control_byte_t

union spinnaker_packet_control_byte_t

The control byte of a SpiNNaker packet.

Definition at line 539 of file spinn_extra.h.

Data Fields
struct mc	mc
struct p2p	p2p
struct nn	nn
struct fr	fr
uchar	value

◆ spinnaker_packet_control_byte_t::common

struct spinnaker_packet_control_byte_t::common

Common fields.

Definition at line 541 of file spinn_extra.h.

Data Fields
uchar	parity: 1	Packet parity.
uchar	payload: 1	Payload-word-present flag.
uchar	timestamp: 2	Timestamp (not used for NN packets)
uchar	type: 2	Should be one of spinnaker_packet_type_t.

◆ spinnaker_packet_control_byte_t::mc

struct spinnaker_packet_control_byte_t::mc

Multicast packet only fields.

Definition at line 554 of file spinn_extra.h.

Data Fields
uchar	emergency_routing: 2	Emergency routing control.

◆ spinnaker_packet_control_byte_t::p2p

struct spinnaker_packet_control_byte_t::p2p

Peer-to-peer packet only fields.

Definition at line 563 of file spinn_extra.h.

Data Fields
uchar	seq_code: 2	Sequence code.

◆ spinnaker_packet_control_byte_t::nn

struct spinnaker_packet_control_byte_t::nn

Nearest-neighbour packet only fields.

Definition at line 572 of file spinn_extra.h.

Data Fields
uchar	route: 3	Routing information.
uchar	mem_or_normal: 1	Type indicator.

◆ spinnaker_packet_control_byte_t::fr

struct spinnaker_packet_control_byte_t::fr

Fixed-route packet only fields.

Definition at line 583 of file spinn_extra.h.

Data Fields
uchar	emergency_routing: 2	Emergency routing control.

◆ comms_tx_control_t

struct comms_tx_control_t

Controls packet transmission.

Definition at line 607 of file spinn_extra.h.

Data Fields
uint	control_byte: 8	control byte of next sent packet
uint	not_full: 1	Tx buffer not full, so it is safe to send a packet.
uint	overrun: 1	Tx buffer overrun (sticky)
uint	full: 1	Tx buffer full (sticky)
uint	empty: 1	Tx buffer empty.

◆ comms_rx_status_t

struct comms_rx_status_t

Indicates packet reception status.

Definition at line 625 of file spinn_extra.h.

Data Fields
uint	multicast: 1	error-free multicast packet received
uint	point_to_point: 1	error-free point-to-point packet received
uint	nearest_neighbour: 1	error-free nearest-neighbour packet received
uint	fixed_route: 1	error-free fixed-route packet received
uint	control_byte: 8	Control byte of last Rx packet.
uint	route: 3	Rx route field from packet.
uint	error_free: 1	Rx packet received without error.
uint	framing_error: 1	Rx packet framing error (sticky)
uint	parity_error: 1	Rx packet parity error (sticky)
uint	received: 1	Rx packet received.

◆ comms_source_addr_t

struct comms_source_addr_t

P2P source address.

Definition at line 653 of file spinn_extra.h.

Data Fields
uint	p2p_source_id: 16	16-bit chip source ID for P2P packets
uint	route: 3	Set 'fake' route in packet.

◆ comms_ctl_t

struct comms_ctl_t

SpiNNaker communications controller registers.

Definition at line 665 of file spinn_extra.h.

Data Fields
comms_tx_control_t	tx_control	Controls packet transmission.
uint	tx_data	32-bit data for transmission
uint	tx_key	Send MC key/P2P dest ID & seq code; writing this commits a send.
comms_rx_status_t	rx_status	Indicates packet reception status.
const uint	rx_data	32-bit received data
const uint	rx_key	Received MC key/P2P source ID & seq code; reading this clears the received packet.
comms_source_addr_t	source_addr	P2P source address.

◆ router_control_t

struct router_control_t

Router control register.

Definition at line 717 of file spinn_extra.h.

Data Fields
uint	route_packets_enable: 1	enable packet routing
uint	error_interrupt_enable: 1	enable error packet interrupt
uint	dump_interrupt_enable: 1	enable dump packet interrupt
uint	count_timestamp_errors: 1	enable count of packet time stamp errors
uint	count_framing_errors: 1	enable count of packet framing errors
uint	count_parity_errors: 1	enable count of packet parity errors
uint	time_phase: 2	time phase (c.f. packet time stamps)
uint	monitor_processor: 5	Monitor Processor ID number.
uint	reinit_wait_counters: 1	re-initialise wait counters
uint	begin_emergency_wait_time: 8	`wait1`; wait time before emergency routing
uint	drop_wait_time: 8	`wait2`; wait time before dropping packet after entering emergency routing

◆ router_status_t

struct router_status_t

Router status.

Definition at line 745 of file spinn_extra.h.

Data Fields
uint	interrupt_active_for_diagnostic_counter: 16	diagnostic counter interrupt active
uint	busy: 1	busy - active packet(s) in Router pipeline
uint	output_stage: 2	Router output stage status (see router_output_stage)
uint	interrupt_active_dump: 1	dump packet interrupt active
uint	interrupt_active_error: 1	error packet interrupt active
uint	interrupt_active: 1	combined Router interrupt request

◆ router_packet_header_t

union router_packet_header_t

Router error/dump header.

Definition at line 777 of file spinn_extra.h.

Data Fields
uint	word	as a whole word

◆ router_packet_header_t::flags

struct router_packet_header_t::flags

Fields in router_packet_header_t.

Definition at line 779 of file spinn_extra.h.

Data Fields
uint	time_phase: 2	time phase when packet received/dumped
uint	control: 8	control byte; really a spinnaker_packet_control_byte_t
uint	route: 3	Rx route field of packet.
uint	time_phase_error: 1	packet time stamp error (error only)
uint	framing_error: 1	packet framing error (error only)
uint	parity_error: 1	packet parity error (error only)

◆ router_packet_header_t::control_field_bits

struct router_packet_header_t::control_field_bits

Critical fields in router_packet_header_t::flags::control.

Definition at line 800 of file spinn_extra.h.

Data Fields
uint	payload: 1	payload-present field from control byte
uint	type: 2	packet-type field from control byte

◆ router_error_status_t

struct router_error_status_t

Router error status.

Definition at line 815 of file spinn_extra.h.

Data Fields
uint	error_count: 16	16-bit saturating error count
uint	time_phase_error: 1	packet time stamp error (sticky)
uint	framing_error: 1	packet framing error (sticky)
uint	parity_error: 1	packet parity error (sticky)
uint	overflow: 1	more than one error packet detected
uint	error: 1	error packet detected

◆ router_dump_outputs_t

struct router_dump_outputs_t

Router dump outputs.

Definition at line 833 of file spinn_extra.h.

Data Fields
uint	link: NUM_LINKS	Tx link transmit error caused packet dump.
uint	processor: NUM_CPUS	Fascicle Processor link error caused dump.

◆ router_dump_status_t

struct router_dump_status_t

Router dump status.

Definition at line 843 of file spinn_extra.h.

Data Fields
uint	link: NUM_LINKS	Tx link error caused dump (sticky)
uint	processor: NUM_CPUS	Fascicle Proc link error caused dump (sticky)
uint	overflow: 1	more than one packet dumped
uint	dumped: 1	packet dumped

◆ router_diagnostic_counter_ctrl_t

struct router_diagnostic_counter_ctrl_t

Router diagnostic counter enable/reset.

Definition at line 857 of file spinn_extra.h.

Data Fields
ushort	enable	enable diagnostic counter 15..0
ushort	reset	write a 1 to reset diagnostic counter 15..0

◆ router_timing_counter_ctrl_t

struct router_timing_counter_ctrl_t

Router timing counter controls.

Definition at line 865 of file spinn_extra.h.

Data Fields
uint	enable_cycle_count: 1	enable cycle counter
uint	enable_emergency_active_count: 1	enable emergency router active cycle counter
uint	enable_histogram: 1	enable histogram
uint	reset_cycle_count: 1	reset cycle counter
uint	reset_emergency_active_count: 1	reset emergency router active cycle counter
uint	reset_histogram: 1	reset histogram

◆ router_diversion_t

struct router_diversion_t

Router diversion rules, used to handle default-routed packets.

Definition at line 885 of file spinn_extra.h.

Data Fields
uint	L0: 2	Diversion rule for link 0.
uint	L1: 2	Diversion rule for link 1.
uint	L2: 2	Diversion rule for link 2.
uint	L3: 2	Diversion rule for link 3.
uint	L4: 2	Diversion rule for link 4.
uint	L5: 2	Diversion rule for link 5.

◆ router_fixed_route_routing_t

struct router_fixed_route_routing_t

Fixed route and nearest neighbour packet routing control.

Definition at line 913 of file spinn_extra.h.

Data Fields
uint	fr_links: NUM_LINKS	The links to route FR packets along.
uint	fr_processors: NUM_CPUS	The physical processors to route FR packets to.
uint	nn_broadcast_links: NUM_LINKS	Nearest-neighbour broadcast link vector.

◆ router_t

struct router_t

SpiNNaker router controller registers.

Definition at line 925 of file spinn_extra.h.

Data Fields
router_control_t	control	Router control register.
const router_status_t	status	Router status.
struct error	error
struct dump	dump
router_diagnostic_counter_ctrl_t	diagnostic_counter_control	diagnostic counter enables
router_timing_counter_ctrl_t	timing_counter_control	timing counter controls
const uint	cycle_count	counts Router clock cycles
const uint	emergency_active_cycle_count	counts emergency router active cycles
const uint	unblocked_count	counts packets that do not wait to be issued
const uint	delay_histogram[16]	packet delay histogram counters
router_diversion_t	diversion	divert default packets
router_fixed_route_routing_t	fixed_route	fixed-route packet routing vector

◆ router_t::error

struct router_t::error

Error-related registers.

Definition at line 931 of file spinn_extra.h.

Data Fields
const router_packet_header_t	header	error packet control byte and flags
const uint	key	error packet routing word
const uint	payload	error packet data payload
const router_error_status_t	status	error packet status

◆ router_t::dump

struct router_t::dump

Packet-dump-related registers.

Definition at line 942 of file spinn_extra.h.

Data Fields
const router_packet_header_t	header	dumped packet control byte and flags
const uint	key	dumped packet routing word
const uint	payload	dumped packet data payload
const router_dump_outputs_t	outputs	dumped packet intended destinations
const router_dump_status_t	status	dumped packet status

◆ router_diagnostic_filter_t

struct router_diagnostic_filter_t

SpiNNaker router diagnostic filter.

Definition at line 973 of file spinn_extra.h.

Data Fields
uint	type: 4	packet type: fr, nn, p2p, mc
uint	emergency_routing: 4	Emergency Routing field = 3, 2, 1 or 0.
uint	emergency_routing_mode: 1	Emergency Routing mode.
uint	pattern_default: 2	default [x1]/non-default [1x] routed packets
uint	pattern_payload: 2	packets with [x1]/without [1x] payload
uint	pattern_local: 2	local [x1]/non-local[1x] packet source
uint	pattern_destination: 9	packet dest (Tx link[5:0], MP, local ¬MP, dump)
uint	counter_event_occurred: 1	counter event has occurred (sticky)
uint	enable_counter_event_interrupt: 1	enable interrupt on counter event
uint	counter_event_interrupt_active: 1	counter interrupt active: I = E AND C

◆ router_multicast_route_t

union router_multicast_route_t

SpiNNaker router multicast route.

Definition at line 1001 of file spinn_extra.h.

Data Fields
uint	value	Overall entry packed as number.

◆ router_multicast_route_t::routes

struct router_multicast_route_t::routes

Where to route a matching entry to.

Definition at line 1003 of file spinn_extra.h.

Data Fields
uint	links: NUM_LINKS	The links to route along.
uint	processors: NUM_CPUS	The physical processors to route to.

◆ router_p2p_table_entry_t

union router_p2p_table_entry_t

A packed word in the P2P routing table.

Definition at line 1035 of file spinn_extra.h.

Data Fields
uint	value	Overall entry packed as number.

◆ router_p2p_table_entry_t::routes

struct router_p2p_table_entry_t::routes

The eight individual routes making up a P2P table entry.

Definition at line 1037 of file spinn_extra.h.

Data Fields
router_p2p_route	route1: 3	First packed route.
router_p2p_route	route2: 3	Second packed route.
router_p2p_route	route3: 3	Third packed route.
router_p2p_route	route4: 3	Fourth packed route.
router_p2p_route	route5: 3	Fifth packed route.
router_p2p_route	route6: 3	Sixth packed route.
router_p2p_route	route7: 3	Seventh packed route.
router_p2p_route	route8: 3	Eighth packed route.

◆ sdram_status_t

struct sdram_status_t

Memory controller status.

Definition at line 1113 of file spinn_extra.h.

Data Fields
uint	status: 2	Config, ready, paused, low-power.
uint	width: 2	Width of external memory: 2’b01 = 32 bits.
uint	ddr: 3	DDR type: 3b’011 = Mobile DDR.
uint	chips: 2	Number of different chip selects (1, 2, 3, 4)
uint	banks: 1	Fixed at 1’b01 = 4 banks on a chip.
uint	monitors: 2	Number of exclusive access monitors (0, 1, 2, 4)

◆ sdram_command_t

struct sdram_command_t

Memory controller command.

Definition at line 1131 of file spinn_extra.h.

Data Fields
uint	command: 3	one of sdram_command

◆ sdram_direct_command_t

struct sdram_direct_command_t

Memory controller direct command.

Used to pass a command directly to a memory device attached to the PL340.

Definition at line 1156 of file spinn_extra.h.

Data Fields
uint	address: 14	address passed to memory device
uint	bank: 2	bank passed to memory device
uint	cmd: 2	command passed to memory device
uint	chip: 2	chip number

◆ sdram_ram_config_t

struct sdram_ram_config_t

Memory configuration.

Definition at line 1185 of file spinn_extra.h.

Data Fields
uint	column: 3	number of column address bits (8-12)
uint	row: 3	number of row address bits (11-16)
uint	auto_precharge_position: 1	position of auto-pre-charge bit (10/8)
uint	power_down_delay: 6	number of memory cycles before auto-power-down
uint	auto_power_down: 1	auto-power-down memory when inactive
uint	stop_clock: 1	stop memory clock when no access
uint	burst: 3	burst length (1, 2, 4, 8, 16)
uint	qos: 3	selects the 4-bit QoS field from the AXI ARID
uint	active: 2	active chips: number for refresh generation

◆ sdram_refresh_t

struct sdram_refresh_t

Memory refresh period.

Definition at line 1209 of file spinn_extra.h.

Data Fields
uint	period: 15	memory refresh period in memory clock cycles

◆ sdram_cas_latency_t

struct sdram_cas_latency_t

Memory CAS latency.

Definition at line 1217 of file spinn_extra.h.

Data Fields
uint	half_cycle: 1	CAS half cycle - must be set to 1’b0.
uint	cas_lat: 3	CAS latency in memory clock cycles.

◆ sdram_timing_config_t

struct sdram_timing_config_t

Memory timimg configuration.

See datasheet for meanings

Definition at line 1228 of file spinn_extra.h.

Data Fields
uint	t_dqss	write to DQS time
uint	t_mrd	mode register command time
uint	t_ras	RAS to precharge delay.
uint	t_rc	active bank x to active bank x delay
uint	t_rcd	RAS to CAS minimum delay.
uint	t_rfc	auto-refresh command time
uint	t_rp	precharge to RAS delay
uint	t_rrd	active bank x to active bank y delay
uint	t_wr	write to precharge delay
uint	t_wtr	write to read delay
uint	t_xp	exit power-down command time
uint	t_xsr	exit self-refresh command time
uint	t_esr	self-refresh command time

◆ sdram_controller_t

struct sdram_controller_t

Memory controller registers.

Definition at line 1258 of file spinn_extra.h.

Data Fields
const sdram_status_t	status	memory controller status
sdram_command_t	command	PL340 command.
sdram_direct_command_t	direct	direct command
sdram_ram_config_t	mem_config	memory configuration
sdram_refresh_t	refresh	refresh period
sdram_cas_latency_t	cas_latency	CAS latency.
sdram_timing_config_t	timing_config	timing configuration

◆ sdram_qos_t

struct sdram_qos_t

Memory QoS settings.

Definition at line 1276 of file spinn_extra.h.

Data Fields
uint	enable: 1	QoS enable.
uint	minimum: 1	minimum QoS
uint	maximum: 8	maximum QoS

◆ sdram_chip_t

struct sdram_chip_t

Memory chip configuration.

Definition at line 1288 of file spinn_extra.h.

Data Fields
uint	mask: 8	address mask
uint	match: 8	address match
uint	orientation: 1	bank-row-column/row-bank-column

◆ sdram_dll_status_t

struct sdram_dll_status_t

Memory delay-locked-loop (DLL) test and status inputs.

Definition at line 1308 of file spinn_extra.h.

Data Fields
uint	meter: 7	Current position of bar-code output.
uint	s0: 1	Strobe 0 faster than Clock.
uint	c0: 1	Clock faster than strobe 0.
uint	s1: 1	Strobe 1 faster than Clock.
uint	c1: 1	Clock faster than strobe 1.
uint	s2: 1	Strobe 2 faster than Clock.
uint	c2: 1	Clock faster than strobe 2.
uint	s3: 1	Strobe 3 faster than Clock.
uint	c3: 1	Clock faster than strobe 3.
uint	decing: 1	Phase comparator is reducing delay.
uint	incing: 1	Phase comparator is increasing delay.
uint	locked: 1	Phase comparator is locked.
uint	R: 1	3-phase bar-code control output
uint	M: 1	3-phase bar-code control output
uint	L: 1	3-phase bar-code control output

◆ sdram_dll_user_config0_t

struct sdram_dll_user_config0_t

Memory delay-locked-loop (DLL) test and control outputs.

Definition at line 1348 of file spinn_extra.h.

Data Fields
uint	s0: 2	Input select for delay line 0 {def, alt, 0, 1}.
uint	s1: 2	Input select for delay line 1 {def, alt, 0, 1}.
uint	s2: 2	Input select for delay line 2 {def, alt, 0, 1}.
uint	s3: 2	Input select for delay line 3 {def, alt, 0, 1}.
uint	s4: 2	Input select for delay line 4 {def, alt, 0, 1}.
uint	s5: 2	Input select for delay line 5 {def, alt, 0, 1}.
uint	test_decing: 1	Force Decing (if ID = 1)
uint	test_incing: 1	Force Incing (if ID = 1)
uint	enable_force_inc_dec: 1	Enable forcing of Incing and Decing.
uint	test_5: 1	Substitute delay line 5 for 4 for testing.
uint	R: 1	Force 3-phase bar-code control inputs.
uint	M: 1	Force 3-phase bar-code control inputs.
uint	L: 1	Force 3-phase bar-code control inputs.
uint	enable_force_lmr: 1	Enable forcing of L, M, R.
uint	enable: 1	Enable DLL (0 = reset DLL)

◆ sdram_dll_user_config1_t

union sdram_dll_user_config1_t

Memory delay-locked-loop (DLL) fine-tune control.

Definition at line 1386 of file spinn_extra.h.

Data Fields
uint	word	Tuning control word.

◆ sdram_dll_user_config1_t::tuning

struct sdram_dll_user_config1_t::tuning

Tuning fields.

Definition at line 1388 of file spinn_extra.h.

Data Fields
uint	tune_0: 4	Fine tuning control on delay line 0.
uint	tune_1: 4	Fine tuning control on delay line 1.
uint	tune_2: 4	Fine tuning control on delay line 2.
uint	tune_3: 4	Fine tuning control on delay line 3.
uint	tune_4: 4	Fine tuning control on delay line 4.
uint	tune_5: 4	Fine tuning control on delay line 5.

◆ sdram_dll_t

struct sdram_dll_t

SDRAM delay-locked-loop (DLL) control registers.

Definition at line 1409 of file spinn_extra.h.

Data Fields
const sdram_dll_status_t	status	Status.
sdram_dll_user_config0_t	config0	Test: control.
sdram_dll_user_config1_t	config1	Test: fine tune.

◆ sc_magic_proc_map_t

struct sc_magic_proc_map_t

System controller processor select.

Definition at line 1464 of file spinn_extra.h.

Data Fields
uint	select: NUM_CPUS	Bit-map for selecting a processor.
uint	security_code: 12	SYSTEM_CONTROLLER_MAGIC_NUMBER to enable write

◆ sc_magic_subsystem_map_t

struct sc_magic_subsystem_map_t

System controller subsystem reset target select.

Definition at line 1474 of file spinn_extra.h.

Data Fields
uint	router: 1	Router.
uint	sdram: 1	PL340 SDRAM controller.
uint	system_noc: 1	System NoC.
uint	comms_noc: 1	Communications NoC.
uint	tx_links: NUM_LINKS	Tx link 0-5.
uint	rx_links: NUM_LINKS	Rx link 0-5.
uint	clock_gen: 1	System AHB & Clock Gen (pulse reset only)
uint	entire_chip: 1	Entire chip (pulse reset only)
uint	security_code: 12	SYSTEM_CONTROLLER_MAGIC_NUMBER to enable write

◆ sc_reset_code_t

struct sc_reset_code_t

System controller last reset status.

Definition at line 1498 of file spinn_extra.h.

Data Fields
uint	reset_code: 3	One of sc_reset_codes.

◆ sc_monitor_id_t

struct sc_monitor_id_t

System controller monitor election control.

Definition at line 1520 of file spinn_extra.h.

Data Fields
uint	monitor_id: 5	Monitor processor identifier.
uint	arbitrate_request: 1	Write 1 to set MP arbitration bit (see system_controller_t::monitor_arbiter)
uint	reset_on_watchdog: 1	Reset Monitor Processor on Watchdog interrupt.
uint	security_code: 12	SYSTEM_CONTROLLER_MAGIC_NUMBER to enable write

◆ sc_misc_control_t

struct sc_misc_control_t

System controller miscellaneous control.

Definition at line 1538 of file spinn_extra.h.

Data Fields
uint	boot_area_map: 1	map System ROM (0) or RAM (1) to Boot area
uint	jtag_on_chip: 1	select on-chip (1) or off-chip (0) control of JTAG pins
uint	test: 1	read value on Test pin
uint	ethermux: 1	read value on Ethermux pin
uint	clk32: 1	read value on Clk32 pin
uint	jtag_tdo: 1	read value on JTAG_TDO pin
uint	jtag_rtck: 1	read value on JTAG_RTCK pin

◆ sc_io_t

union sc_io_t

System controller general chip I/O pin access.

Definition at line 1560 of file spinn_extra.h.

Data Fields
uint	gpio	GPIO pins.

◆ sc_io_t::io_bits

struct sc_io_t::io_bits

Control over I/O pins used for non-GPIO purposes.

Definition at line 1562 of file spinn_extra.h.

Data Fields
uint	ethernet_receive: 4	Ethernet MII RxD port.
uint	ethernet_transmit: 4	Ethernet MII TxD port.
uint	jtag: 4	JTAG interface.
uint	sdram: 3	On-package SDRAM control.

◆ sc_pll_control_t

struct sc_pll_control_t

System controller phase-locked-loop control.

Definition at line 1581 of file spinn_extra.h.

Data Fields
uint	input_multiplier: 6	input clock multiplier
uint	output_divider: 6	output clock divider
uint	freq_range: 2	frequency range (see sc_frequency_range)
uint	power_up: 1	Power UP.

◆ sc_clock_mux_t

struct sc_clock_mux_t

System controller clock multiplexing control.

Definition at line 1615 of file spinn_extra.h.

Data Fields
uint	pa: 2	clock selector for A CPUs (1 2 4 7 8 11 13 14 16); see sc_clock_source
uint	adiv: 2	divide CPU clock A by Adiv+1 (= 1-4)
uint	pb: 2	clock selector for B CPUs (0 3 5 6 9 10 12 15 17); see sc_clock_source
uint	bdiv: 2	divide CPU clock B by Bdiv+1 (= 1-4)
uint	mem: 2	clock selector for SDRAM; see sc_clock_source
uint	mdiv: 2	divide SDRAM clock by Mdiv+1 (= 1-4)
uint	rtr: 2	clock selector for Router; see sc_clock_source
uint	rdiv: 2	divide Router clock by Rdiv+1 (= 1-4)
uint	sys: 2	clock selector for System AHB components; see sc_clock_source
uint	sdiv: 2	divide System AHB clock by Sdiv+1 (= 1-4)
uint	invert_b: 1	invert CPU clock B

◆ sc_sleep_status_t

struct sc_sleep_status_t

System controller sleep status.

Definition at line 1665 of file spinn_extra.h.

Data Fields
uint	status: NUM_CPUS	ARM968 STANDBYWFI signal for each core.

◆ sc_temperature_t

struct sc_temperature_t

System controller temperature status/control.

Definition at line 1673 of file spinn_extra.h.

Data Fields
uint	temperature: 24	temperature sensor reading
uint	sample_finished: 1	temperature measurement finished
uint	start: 1	start temperature measurement

◆ sc_mutex_bit_t

struct sc_mutex_bit_t

System controller mutex/interlock.

Definition at line 1685 of file spinn_extra.h.

Data Fields
uint	bit: 1	The only relevant bit in the word.

◆ sc_link_disable_t

struct sc_link_disable_t

System controller link and router control.

Definition at line 1693 of file spinn_extra.h.

Data Fields
uint	rx_disable: NUM_LINKS	disables the corresponding link receiver
uint	tx_disable: NUM_LINKS	disables the corresponding link transmitter
uint	parity_control: 1	Router parity control.
uint	security_code: 12	SYSTEM_CONTROLLER_MAGIC_NUMBER to enable write

◆ system_controller_t

struct system_controller_t

System controller registers.

Definition at line 1715 of file spinn_extra.h.

Data Fields
const uint	chip_id	Chip ID register (hardwired)
sc_magic_proc_map_t	processor_disable	Each bit disables a processor.
sc_magic_proc_map_t	set_cpu_irq	Writing a 1 sets a processor’s interrupt line.
sc_magic_proc_map_t	clear_cpu_irq	Writing a 1 clears a processor’s interrupt line.
uint	set_cpu_ok	Writing a 1 sets a CPU OK bit.
uint	clear_cpu_ok	Writing a 1 clears a CPU OK bit.
sc_magic_proc_map_t	cpu_soft_reset_level	Level control of CPU resets.
sc_magic_proc_map_t	cpu_hard_reset_level	Level control of CPU node resets.
sc_magic_subsystem_map_t	subsystem_reset_level	Level control of subsystem resets.
sc_magic_proc_map_t	cpu_soft_reset_pulse	Pulse control of CPU resets.
sc_magic_proc_map_t	cpu_hard_reset_pulse	Pulse control of CPU node resets.
sc_magic_subsystem_map_t	subsystem_reset_pulse	Pulse control of subsystem resets.
const sc_reset_code_t	reset_code	Indicates cause of last chip reset.
sc_monitor_id_t	monitor_id	ID of Monitor Processor.
sc_misc_control_t	misc_control	Miscellaneous control bits.
sc_io_t	gpio_pull_up_down_enable	General-purpose IO pull up/down enable.
sc_io_t	io_port	I/O pin output register.
sc_io_t	io_direction	External I/O pin is input (1) or output (0)
sc_io_t	io_set	Writing a 1 sets IO register bit.
sc_io_t	io_clear	Writing a 1 clears IO register bit.
sc_pll_control_t	pll1_freq_control	PLL1 frequency control.
sc_pll_control_t	pll2_freq_control	PLL2 frequency control.
uint	set_flags	Set flags register.
uint	reset_flags	Reset flags register.
sc_clock_mux_t	clock_mux_control	Clock multiplexer controls.
const sc_sleep_status_t	cpu_sleep	CPU sleep (awaiting interrupt) status.
sc_temperature_t	temperature[_NUM_TEMPS]	Temperature sensor registers [2:0].
const sc_mutex_bit_t	monitor_arbiter[_NUM_ARBITERS]	Read sensitive semaphores to determine MP.
const sc_mutex_bit_t	test_and_set[_NUM_LOCK_REGISTERS]	Test & Set registers for general software use.
const sc_mutex_bit_t	test_and_clear[_NUM_LOCK_REGISTERS]	Test & Clear registers for general software use.
sc_link_disable_t	link_disable	Disables for Tx and Rx link interfaces.

◆ ethernet_general_command_t

struct ethernet_general_command_t

Ethernet general command.

Definition at line 1818 of file spinn_extra.h.

Data Fields
uint	transmit: 1	Transmit system enable.
uint	receive: 1	Receive system enable.
uint	loopback: 1	Loopback enable.
uint	receive_error_filter: 1	Receive error filter enable.
uint	receive_unicast: 1	Receive unicast packets enable.
uint	receive_multicast: 1	Receive multicast packets enable.
uint	receive_broadcast: 1	Receive broadcast packets enable.
uint	receive_promiscuous: 1	Receive promiscuous packets enable.
uint	receive_vlan: 1	Receive VLAN enable.
uint	reset_drop_counter: 1	Reset receive dropped frame count (ethernet_general_status_t::drop_counter)
uint	hardware_byte_reorder_disable: 1	Disable hardware byte reordering.

◆ ethernet_general_status_t

struct ethernet_general_status_t

Ethernet general status.

Definition at line 1846 of file spinn_extra.h.

Data Fields
uint	transmit_active: 1	Transmit MII interface active.
uint	unread_counter: 6	Received unread frame count.
uint	drop_counter: 16	Receive dropped frame count.

◆ ethernet_tx_length_t

struct ethernet_tx_length_t

Ethernet frame transmit length.

Definition at line 1858 of file spinn_extra.h.

Data Fields
uint	tx_length: 11	Length of transmit frame (60 - 1514 bytes)

◆ ethernet_phy_control_t

struct ethernet_phy_control_t

Ethernet PHY (physical layer) control.

Definition at line 1872 of file spinn_extra.h.

Data Fields
uint	reset: 1	PHY reset (active low)
uint	smi_input: 1	SMI data input.
uint	smi_output: 1	SMI data output.
uint	smi_out_enable: 1	SMI data output enable.
uint	smi_clock: 1	SMI clock (active rising)
uint	irq_invert_disable: 1	PHY IRQn invert disable.

◆ ethernet_interrupt_clear_t

struct ethernet_interrupt_clear_t

Ethernet interrupt clear register.

Definition at line 1890 of file spinn_extra.h.

Data Fields
uint	transmit: 1	Clear transmit interrupt request.
uint	receive: 1	Clear receive interrupt request.

◆ ethernet_receive_pointer_t

struct ethernet_receive_pointer_t

Ethernet receive data pointer.

Definition at line 1902 of file spinn_extra.h.

Data Fields
uint	ptr: 12	Receive frame buffer read pointer.
uint	rollover: 1	Rollover bit - toggles on address wrap-around.

◆ ethernet_receive_descriptor_pointer_t

struct ethernet_receive_descriptor_pointer_t

Ethernet receive descriptor pointer.

Definition at line 1912 of file spinn_extra.h.

Data Fields
uint	ptr: 6	Receive descriptor read pointer.
uint	rollover: 1	Rollover bit - toggles on address wrap-around.

◆ ethernet_controller_t

struct ethernet_controller_t

Ethernet controller registers.

Definition at line 1922 of file spinn_extra.h.

Data Fields
ethernet_general_command_t	command	General command.
const ethernet_general_status_t	status	General status.
ethernet_tx_length_t	transmit_length	Transmit frame length.
uint	transmit_command	Transmit command; any value commits transmit.
uint	receive_command	Receive command; any value completes receive.
uint64	mac_address	MAC address; low 48 bits only.
ethernet_phy_control_t	phy_control	PHY control.
ethernet_interrupt_clear_t	interrupt_clear	Interrupt clear.
const ethernet_receive_pointer_t	receive_read	Receive frame buffer read pointer.
const ethernet_receive_pointer_t	receive_write	Receive frame buffer write pointer.
const ethernet_receive_descriptor_pointer_t	receive_desc_read	Receive descriptor read pointer.
const ethernet_receive_descriptor_pointer_t	receive_desc_write	Receive descriptor write pointer.

◆ ethernet_receive_descriptor_t

struct ethernet_receive_descriptor_t

Ethernet received message descriptor.

Warning: Cannot find description of rest of this structure; SCAMP only uses one field. Datasheet refers document that appears to be lost.

Definition at line 1954 of file spinn_extra.h.

Data Fields
uint	length: 11	Received packet length.

◆ watchdog_control_t

struct watchdog_control_t

Watchdog timer control register.

Definition at line 1995 of file spinn_extra.h.

Data Fields
uint	interrupt_enable: 1	Enable Watchdog counter and interrupt (1)
uint	reset_enable: 1	Enable the Watchdog reset output (1)

◆ watchdog_status_t

struct watchdog_status_t

Watchdog timer status registers.

Definition at line 2005 of file spinn_extra.h.

Data Fields
uint	interrupted: 1	True if interrupt asserted.

◆ watchdog_lock_t

union watchdog_lock_t

Watchdog timer lock register.

Definition at line 2013 of file spinn_extra.h.

Data Fields
uint	whole_value	Whole value of lock; see watchdog_lock_codes.

◆ watchdog_lock_t::fields

struct watchdog_lock_t::fields

The fields in the lock register.

Definition at line 2015 of file spinn_extra.h.

Data Fields
uint	lock: 1	Write access enabled (0) or disabled (1)
uint	magic: 31	Access control code.

◆ watchdog_controller_t

struct watchdog_controller_t

Watchdog timer control registers.

Definition at line 2034 of file spinn_extra.h.

Data Fields
uint	load	Count load register.
const uint	value	Current count value.
watchdog_control_t	control	Control register.
uint	interrupt_clear	Interrupt clear register; any written value will do.
const watchdog_status_t	raw_status	Raw interrupt status register.
const watchdog_status_t	masked_status	Masked interrupt status register.
watchdog_lock_t	lock	Lock register.

Macro Definition Documentation

◆ ASSERT_WORD_SIZED

#define ASSERT_WORD_SIZED ( type_ident )

Value:

    static inline void __static_word_sized_assert_ ## type_ident (void) { \
        _Static_assert(sizeof(type_ident) == sizeof(uint),              \
                #type_ident " must be the same size as a word");        \
    }

Generates valid code if the named type is one word long, and invalid code otherwise.

Parameters

type_ident The name of the type that we are asserting is one word long. This macro assumes that it's a name, and not just any old type.

Definition at line 60 of file spinn_extra.h.

Typedef Documentation

◆ vic_interrupt_handler_t

typedef void(* vic_interrupt_handler_t) (void)

The type of an interrupt handler.

Definition at line 102 of file spinn_extra.h.

Enumeration Type Documentation

◆ timer_pre_divide

enum timer_pre_divide

Values for timer_control_t::pre_divide.

Enumerator
TIMER_PRE_DIVIDE_1	Divide by 1.
TIMER_PRE_DIVIDE_16	Divide by 16.
TIMER_PRE_DIVIDE_256	Divide by 256.

Definition at line 264 of file spinn_extra.h.

◆ dma_direction_t

enum dma_direction_t

DMA transfer direction, see dma_description_t::direction.

Enumerator
DMA_DIRECTION_READ	read from system bus (SDRAM)
DMA_DIRECTION_WRITE	write to system bus (SDRAM)

Definition at line 352 of file spinn_extra.h.

◆ dma_transfer_unit_t

enum dma_transfer_unit_t

DMA burst width, see dma_description_t::width.

Enumerator
DMA_TRANSFER_WORD	Transfer in words.
DMA_TRANSFER_DOUBLE_WORD	Transfer in double-words.

Definition at line 360 of file spinn_extra.h.

◆ spinnaker_packet_type_t

enum spinnaker_packet_type_t

SpiNNaker packet type codes.

Enumerator
SPINNAKER_PACKET_TYPE_MC	Multicast packet.
SPINNAKER_PACKET_TYPE_P2P	Peer-to-peer packet.
SPINNAKER_PACKET_TYPE_NN	Nearest-neighbour packet.
SPINNAKER_PACKET_TYPE_FR	Fixed-route packet.

Definition at line 595 of file spinn_extra.h.

◆ router_output_stage

enum router_output_stage

Stages in router_status_t::output_stage.

Enumerator
ROUTER_OUTPUT_STAGE_EMPTY	output stage is empty
ROUTER_OUTPUT_STAGE_FULL	output stage is full but unblocked
ROUTER_OUTPUT_STAGE_WAIT1	output stage is blocked in `wait1`
ROUTER_OUTPUT_STAGE_WAIT2	output stage is blocked in `wait2`

Definition at line 765 of file spinn_extra.h.

◆ router_diversion_rule_t

enum router_diversion_rule_t

Diversion rules for the fields of router_diversion_t.

Enumerator
ROUTER_DIVERSION_NORMAL	Send on default route.
ROUTER_DIVERSION_MONITOR	Divert to local monitor.
ROUTER_DIVERSION_DESTROY	Destroy default-routed packets.

Definition at line 903 of file spinn_extra.h.

◆ router_p2p_route

enum router_p2p_route

The possible values of a P2P route.

Enumerator
ROUTER_P2P_ROUTE_E	Route east.
ROUTER_P2P_ROUTE_NE	Route north-east.
ROUTER_P2P_ROUTE_N	Route north.
ROUTER_P2P_ROUTE_W	Route west.
ROUTER_P2P_ROUTE_SW	Route south-west.
ROUTER_P2P_ROUTE_S	Route south.
ROUTER_P2P_ROUTE_DROP	Drop packet.
ROUTER_P2P_ROUTE_MONITOR	Send to monitor (as determined by router_control_t::monitor_processor)

Definition at line 1014 of file spinn_extra.h.

◆ sdram_command

enum sdram_command

Memory controller commands, for sdram_command_t::command.

Todo:: Verify SDRAM_CTL_SLEEP, SDRAM_CTL_WAKE, SDRAM_CTL_ACTIVE_PAUSE

Enumerator
SDRAM_CTL_GO	Go.
SDRAM_CTL_SLEEP	Sleep.
SDRAM_CTL_WAKE	Wake.
SDRAM_CTL_PAUSE	Pause.
SDRAM_CTL_CONFIG	Configure.
SDRAM_CTL_ACTIVE_PAUSE	Active Pause.

Definition at line 1138 of file spinn_extra.h.

◆ sdram_direct_command

enum sdram_direct_command

Memory direct commands, for sdram_direct_command_t::cmd.

Codes from SARK (sark_hw.c, pl340_init)

Enumerator
SDRAM_DIRECT_PRECHARGE	Precharge.
SDRAM_DIRECT_AUTOREFRESH	Auto-Refresh.
SDRAM_DIRECT_MODEREG	Mode Register.
SDRAM_DIRECT_NOP	No-op.

Definition at line 1173 of file spinn_extra.h.

◆ sdram_register_maxima

enum sdram_register_maxima

Maximum register IDs.

Enumerator
SDRAM_QOS_MAX	Maximum memory QoS register.
SDRAM_CHIP_MAX	Maximum memory chip configuration register.

Definition at line 1300 of file spinn_extra.h.

◆ sc_reset_codes

enum sc_reset_codes

System controller chip reset reasons.

Enumerator
SC_RESET_CODE_POR	Power-on reset.
SC_RESET_CODE_WDR	Watchdog reset.
SC_RESET_CODE_UR	User reset.
SC_RESET_CODE_REC	Reset entire chip (sc_magic_subsystem_map_t::entire_chip)
SC_RESET_CODE_WDI	Watchdog interrupt.

Definition at line 1506 of file spinn_extra.h.

◆ sc_frequency_range

enum sc_frequency_range

Frequency range constants for sc_pll_control_t::freq_range.

Enumerator
FREQ_25_50	25-50 MHz
FREQ_50_100	50-100 MHz
FREQ_100_200	100-200 MHz
FREQ_200_400	200-400 MHz

Definition at line 1603 of file spinn_extra.h.

◆ sc_clock_source

enum sc_clock_source

System controller clock sources.

Used for sc_clock_mux_t::pa, sc_clock_mux_t::pb, sc_clock_mux_t::mem, sc_clock_mux_t::rtr, sc_clock_mux_t::sys

Enumerator
CLOCK_SRC_EXT	external 10MHz clock input
CLOCK_SRC_PLL1	PLL1.
CLOCK_SRC_PLL2	PLL2.
CLOCK_SRC_EXT4	external 10MHz clock divided by 4

Definition at line 1653 of file spinn_extra.h.

◆ sc_magic

enum sc_magic

System controller magic numbers.

Enumerator
SYSTEM_CONTROLLER_MAGIC_NUMBER	Magic number for enabling writing to critical fields.

Definition at line 1783 of file spinn_extra.h.

◆ ethernet_tx_length_limits

enum ethernet_tx_length_limits

Limits of ethernet_tx_length_t::tx_length.

Enumerator
ETHERNET_TX_LENGTH_MIN	Minimum length of an ethernet frame.
ETHERNET_TX_LENGTH_MAX	Maximum length of an ethernet frame.

Definition at line 1864 of file spinn_extra.h.

◆ watchdog_lock_codes

enum watchdog_lock_codes

Watchdog timer lock codes, for watchdog_lock_t::whole_value.

Enumerator
WATCHDOG_LOCK_RESET	Put the watchdog timer into normal mode.
WATCHDOG_LOCK_MAGIC	Unlock the watchdog timer for configuration.

Definition at line 2026 of file spinn_extra.h.

Variable Documentation

◆ vic_control

volatile vic_control_t* const vic_control

static

Initial value:

=
        
        (vic_control_t *) VIC_BASE_UNBUF

VIC registers.

Definition at line 220 of file spinn_extra.h.

◆ vic_interrupt_vector

volatile vic_interrupt_handler_t* const vic_interrupt_vector

static

Initial value:

=

(vic_interrupt_handler_t *) (VIC_BASE + 0x100)

vic_interrupt_handler_t

void(* vic_interrupt_handler_t)(void)

The type of an interrupt handler.

Definition spinn_extra.h:102

VIC interrupt handlers. Array of 32 elements.

Definition at line 224 of file spinn_extra.h.

◆ vic_interrupt_control

volatile vic_vector_control_t* const vic_interrupt_control

static

Initial value:

=

(vic_vector_control_t *) (VIC_BASE + 0x200)

vic_vector_control_t

VIC individual vector control.

Definition spinn_extra.h:206

VIC individual interrupt control. Array of 32 elements.

Definition at line 227 of file spinn_extra.h.

◆ timer1_control

volatile timer_controller_t* const timer1_control

static

Initial value:

=

(timer_controller_t *) TIMER1_BASE

timer_controller_t

Timer controller registers.

Definition spinn_extra.h:282

Timer 1 control registers.

Definition at line 305 of file spinn_extra.h.

◆ timer2_control

volatile timer_controller_t* const timer2_control

static

Initial value:

=

(timer_controller_t *) TIMER2_BASE

Timer 2 control registers.

Definition at line 308 of file spinn_extra.h.

◆ dma_control

volatile dma_t* const dma_control = (dma_t *) DMA_BASE

static

DMA control registers.

Definition at line 527 of file spinn_extra.h.

◆ comms_control

volatile comms_ctl_t* const comms_control = (comms_ctl_t *) CC_BASE

static

Communications controller registers.

Definition at line 690 of file spinn_extra.h.

◆ router_control

volatile router_t* const router_control = (router_t *) RTR_BASE

static

Router controller registers.

Definition at line 1073 of file spinn_extra.h.

◆ router_diagnostic_filter

volatile router_diagnostic_filter_t* const router_diagnostic_filter

static

Initial value:

=

(router_diagnostic_filter_t *) (RTR_BASE + 0x200)

router_diagnostic_filter_t

SpiNNaker router diagnostic filter.

Definition spinn_extra.h:973

Router diagnostic filters.

Definition at line 1075 of file spinn_extra.h.

◆ router_diagnostic_counter

volatile uint* const router_diagnostic_counter

static

Initial value:

=

(uint *) (RTR_BASE + 0x300)

Router diagnostic counters.

Definition at line 1078 of file spinn_extra.h.

◆ router_multicast_table

volatile router_multicast_route_t* const router_multicast_table

static

Initial value:

=

(router_multicast_route_t *) RTR_MCRAM_BASE

router_multicast_route_t

SpiNNaker router multicast route.

Definition spinn_extra.h:1001

Router multicast route table.

Definition at line 1081 of file spinn_extra.h.

◆ router_key_table

Initial value:

=

(watchdog_controller_t *) WDOG_BASE

watchdog_controller_t

Watchdog timer control registers.

Definition spinn_extra.h:2034

Watchdog timer controller registers.

Definition at line 2058 of file spinn_extra.h.

Data Structures

Macros

6. Counter/Timer

7. DMA Controller

8. Communications controller

10. SpiNNaker Router

13. SDRAM interface

14. System Controller

15. Ethernet Media-independent interface (MII)

16. Watchdog timer

5. Vectored Interrupt Controller

Detailed Description

Data Structure Documentation

◆ vic_mask_t

◆ vic_mask_t::interrupt_bits

◆ vic_control_t

◆ vic_vector_control_t

◆ timer_control_t

◆ timer_interrupt_status_t

◆ timer_controller_t

◆ dma_description_t

◆ dma_control_t

◆ dma_status_t

◆ dma_global_control_t

◆ dma_timeout_t

◆ dma_stats_control_t

◆ dma_t

◆ spinnaker_packet_control_byte_t

◆ spinnaker_packet_control_byte_t::common

◆ spinnaker_packet_control_byte_t::mc

◆ spinnaker_packet_control_byte_t::p2p

◆ spinnaker_packet_control_byte_t::nn

◆ spinnaker_packet_control_byte_t::fr

◆ comms_tx_control_t

◆ comms_rx_status_t

◆ comms_source_addr_t

◆ comms_ctl_t

◆ router_control_t

◆ router_status_t

◆ router_packet_header_t

◆ router_packet_header_t::flags

◆ router_packet_header_t::control_field_bits

◆ router_error_status_t

◆ router_dump_outputs_t

◆ router_dump_status_t

◆ router_diagnostic_counter_ctrl_t

◆ router_timing_counter_ctrl_t

◆ router_diversion_t

◆ router_fixed_route_routing_t

◆ router_t

◆ router_t::error

◆ router_t::dump

◆ router_diagnostic_filter_t

◆ router_multicast_route_t

◆ router_multicast_route_t::routes

◆ router_p2p_table_entry_t

◆ router_p2p_table_entry_t::routes

◆ sdram_status_t

◆ sdram_command_t

◆ sdram_direct_command_t

◆ sdram_ram_config_t

◆ sdram_refresh_t

◆ sdram_cas_latency_t

◆ sdram_timing_config_t

◆ sdram_controller_t

◆ sdram_qos_t

◆ sdram_chip_t

◆ sdram_dll_status_t

◆ sdram_dll_user_config0_t

◆ sdram_dll_user_config1_t

◆ sdram_dll_user_config1_t::tuning

◆ sdram_dll_t

◆ sc_magic_proc_map_t

◆ sc_magic_subsystem_map_t

◆ sc_reset_code_t

◆ sc_monitor_id_t

◆ sc_misc_control_t

◆ sc_io_t

◆ sc_io_t::io_bits

◆ sc_pll_control_t