SpiNNFrontEndCommon
7.2.2
Common support code for user-facing front end systems.
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front_end_common_lib
include
spinn_extra.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2019 The University of Manchester
3
*
4
* Licensed under the Apache License, Version 2.0 (the "License");
5
* you may not use this file except in compliance with the License.
6
* You may obtain a copy of the License at
7
*
8
* https://www.apache.org/licenses/LICENSE-2.0
9
*
10
* Unless required by applicable law or agreed to in writing, software
11
* distributed under the License is distributed on an "AS IS" BASIS,
12
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
* See the License for the specific language governing permissions and
14
* limitations under the License.
15
*/
16
17
// ------------------------------------------------------------------------
29
// ------------------------------------------------------------------------
30
31
#ifndef __SPINN_EXTRA_H__
32
#define __SPINN_EXTRA_H__
33
34
#include <
spinnaker.h
>
35
#include <stdbool.h>
36
37
#ifndef DOXYGEN
38
// Hack for better naming in doxygen while avoiding warnings when building
39
#define DOXYNAME(x)
/* nothing */
40
#endif
41
42
#if defined(__GNUC__) && __GNUC__ < 6
43
// This particular warning (included in -Wextra) is retarded wrong for client
44
// code of this file. Only really a problem on Travis.
45
#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
46
#endif
// __GNUC__
47
60
#define ASSERT_WORD_SIZED(type_ident) \
61
static inline void __static_word_sized_assert_ ## type_ident (void) { \
62
_Static_assert(sizeof(type_ident) == sizeof(uint), \
63
#type_ident " must be the same size as a word"); \
64
}
65
66
// ---------------------------------------------------------------------
67
// 1. Chip Organization
68
69
// No registers
70
71
// ---------------------------------------------------------------------
72
// 2. System Architecture
73
74
// No registers
75
76
// ---------------------------------------------------------------------
77
// 3. ARM968 Processing Subsystem
78
79
// No registers
80
81
// ---------------------------------------------------------------------
82
// 4. ARM 968
83
84
// No special registers here
85
86
// ---------------------------------------------------------------------
100
102
typedef
void (*
vic_interrupt_handler_t
) (void);
103
105
typedef
union
{
107
struct
DOXYNAME(interrupt_bits) {
109
uint
watchdog
: 1;
111
uint
software
: 1;
113
uint
comm_rx
: 1;
115
uint
comm_tx
: 1;
117
uint
timer1
: 1;
119
uint
timer2
: 1;
121
uint
cc_rx_ready
: 1;
123
uint
cc_rx_parity_error
: 1;
125
uint
cc_rx_framing_error
: 1;
127
uint
cc_tx_full
: 1;
129
uint
cc_tx_overflow
: 1;
131
uint
cc_tx_empty
: 1;
133
uint
dma_done
: 1;
135
uint
dma_error
: 1;
137
uint
dma_timeout
: 1;
139
uint
router_diagnostic
: 1;
141
uint
router_dump
: 1;
143
uint
router_error
: 1;
145
uint
cpu
: 1;
147
uint
ethernet_tx
: 1;
149
uint
ethernet_rx
: 1;
151
uint
ethernet_phy
: 1;
153
uint
slow_clock
: 1;
155
uint
cc_tx_not_full
: 1;
157
uint
cc_rx_mc
: 1;
159
uint
cc_rx_p2p
: 1;
161
uint
cc_rx_nn
: 1;
163
uint
cc_rx_fr
: 1;
165
uint
int0
: 1;
167
uint
int1
: 1;
169
uint
gpio8
: 1;
171
uint
gpio9
: 1;
172
};
174
uint
value
;
175
}
vic_mask_t
;
176
178
typedef
struct
{
180
const
vic_mask_t
irq_status
;
182
const
vic_mask_t
fiq_status
;
184
const
vic_mask_t
raw_status
;
186
vic_mask_t
int_select
;
188
vic_mask_t
int_enable
;
190
vic_mask_t
int_disable
;
192
vic_mask_t
soft_int_enable
;
194
vic_mask_t
soft_int_disable
;
196
bool
protection
;
197
// padding
198
const
uint
_padding[3];
200
vic_interrupt_handler_t
vector_address
;
202
vic_interrupt_handler_t
default_vector_address
;
203
}
vic_control_t
;
204
206
typedef
struct
{
208
uint
source
: 5;
210
uint
enable
: 1;
211
// padding
212
uint
: 26;
213
}
vic_vector_control_t
;
214
215
ASSERT_WORD_SIZED
(
vic_mask_t
);
216
ASSERT_WORD_SIZED
(
vic_interrupt_handler_t
);
217
ASSERT_WORD_SIZED
(
vic_vector_control_t
);
218
220
static
volatile
vic_control_t
*
const
vic_control
=
221
// NB unbuffered!
222
(
vic_control_t
*) VIC_BASE_UNBUF;
224
static
volatile
vic_interrupt_handler_t
*
const
vic_interrupt_vector
=
225
(
vic_interrupt_handler_t
*) (VIC_BASE + 0x100);
227
static
volatile
vic_vector_control_t
*
const
vic_interrupt_control
=
228
(
vic_vector_control_t
*) (VIC_BASE + 0x200);
229
231
232
// ---------------------------------------------------------------------
242
244
typedef
struct
{
246
uint
one_shot
: 1;
248
uint
size
: 1;
250
uint
pre_divide
: 2;
251
// padding
252
uint
: 1;
254
uint
interrupt_enable
: 1;
256
uint
periodic_mode
: 1;
258
uint
enable
: 1;
259
// padding
260
uint
: 24;
261
}
timer_control_t
;
262
264
enum
timer_pre_divide
{
266
TIMER_PRE_DIVIDE_1
= 0,
268
TIMER_PRE_DIVIDE_16
= 1,
270
TIMER_PRE_DIVIDE_256
= 2
271
};
272
274
typedef
struct
{
276
uint
status
: 1;
277
// padding
278
uint
: 31;
279
}
timer_interrupt_status_t
;
280
282
typedef
struct
{
284
uint
load_value
;
286
const
uint
current_value
;
288
timer_control_t
control
;
290
uint
interrupt_clear
;
292
const
timer_interrupt_status_t
raw_interrupt_status
;
294
const
timer_interrupt_status_t
masked_interrupt_status
;
296
uint
background_load_value
;
297
// padding
298
uint
_dummy;
299
}
timer_controller_t
;
300
301
ASSERT_WORD_SIZED
(
timer_control_t
);
302
ASSERT_WORD_SIZED
(
timer_interrupt_status_t
);
303
305
static
volatile
timer_controller_t
*
const
timer1_control
=
306
(
timer_controller_t
*) TIMER1_BASE;
308
static
volatile
timer_controller_t
*
const
timer2_control
=
309
(
timer_controller_t
*) TIMER2_BASE;
310
312
313
// ---------------------------------------------------------------------
328
330
typedef
struct
{
332
uint
_zeroes : 2;
334
uint
length_words
: 15;
335
// padding
336
uint
: 2;
338
uint
direction
: 1;
340
uint
crc
: 1;
342
uint
burst
: 3;
344
uint
width
: 1;
346
uint
privilege
: 1;
348
uint
transfer_id
: 6;
349
}
dma_description_t
;
350
352
enum
dma_direction_t
{
354
DMA_DIRECTION_READ
,
356
DMA_DIRECTION_WRITE
357
};
358
360
enum
dma_transfer_unit_t
{
362
DMA_TRANSFER_WORD
,
364
DMA_TRANSFER_DOUBLE_WORD
365
};
366
368
typedef
struct
{
370
uint
uncommit
: 1;
372
uint
abort
: 1;
374
uint
restart
: 1;
376
uint
clear_done_int
: 1;
378
uint
clear_timeout_int
: 1;
380
uint
clear_write_buffer_int
: 1;
381
// padding
382
uint
: 26;
383
}
dma_control_t
;
384
386
typedef
struct
{
388
uint
transferring
: 1;
390
uint
paused
: 1;
392
uint
queued
: 1;
394
uint
write_buffer_full
: 1;
396
uint
write_buffer_active
: 1;
397
// padding
398
uint
: 5;
400
uint
transfer_done
: 1;
402
uint
transfer2_done
: 1;
404
uint
timeout
: 1;
406
uint
crc_error
: 1;
408
uint
tcm_error
: 1;
410
uint
axi_error
: 1;
412
uint
user_abort
: 1;
414
uint
soft_reset
: 1;
415
// not allocated
416
uint
: 2;
418
uint
write_buffer_error
: 1;
419
// padding
420
uint
: 3;
422
uint
processor_id
: 8;
423
}
dma_status_t
;
424
426
typedef
struct
{
428
uint
bridge_buffer_enable
: 1;
429
// padding
430
uint
: 9;
432
uint
transfer_done_interrupt
: 1;
434
uint
transfer2_done_interrupt
: 1;
436
uint
timeout_interrupt
: 1;
438
uint
crc_error_interrupt
: 1;
440
uint
tcm_error_interrupt
: 1;
442
uint
axi_error_interrupt
: 1;
444
uint
user_abort_interrupt
: 1;
446
uint
soft_reset_interrupt
: 1;
447
// not allocated
448
uint
: 2;
450
uint
write_buffer_error_interrupt
: 1;
451
// padding
452
uint
: 10;
454
uint
timer
: 1;
455
}
dma_global_control_t
;
456
458
typedef
struct
{
460
uint
_zeroes : 5;
462
uint
value
: 5;
463
// padding
464
uint
: 22;
465
}
dma_timeout_t
;
466
468
typedef
struct
{
470
uint
enable
: 1;
472
uint
clear
: 1;
473
// padding
474
uint
: 30;
475
}
dma_stats_control_t
;
476
478
typedef
struct
{
479
// padding
480
const
uint
_unused1[1];
482
void
*
sdram_address
;
484
void
*
tcm_address
;
486
dma_description_t
description
;
488
dma_control_t
control
;
490
const
dma_status_t
status
;
492
dma_global_control_t
global_control
;
494
const
uint
crcc
;
496
const
uint
crcr
;
498
dma_timeout_t
timeout
;
500
dma_stats_control_t
statistics_control
;
501
// padding
502
const
uint
_unused2[5];
504
const
uint
statistics[8];
505
// padding
506
const
uint
_unused3[41];
508
const
void
*
current_sdram_address
;
510
const
void
*
current_tcm_address
;
512
const
dma_description_t
current_description
;
513
// padding
514
const
uint
_unused4[29];
516
uint
crc_polynomial[32];
517
}
dma_t
;
518
519
ASSERT_WORD_SIZED
(
dma_description_t
);
520
ASSERT_WORD_SIZED
(
dma_control_t
);
521
ASSERT_WORD_SIZED
(
dma_status_t
);
522
ASSERT_WORD_SIZED
(
dma_global_control_t
);
523
ASSERT_WORD_SIZED
(
dma_timeout_t
);
524
ASSERT_WORD_SIZED
(
dma_stats_control_t
);
525
527
static
volatile
dma_t
*
const
dma_control
= (
dma_t
*) DMA_BASE;
528
530
531
// ---------------------------------------------------------------------
537
539
typedef
union
{
541
struct
DOXYNAME(common) {
543
uchar
parity
: 1;
545
uchar
payload
: 1;
547
uchar
timestamp
: 2;
548
// padding
549
uchar
: 2;
551
uchar
type
: 2;
552
};
554
struct
DOXYNAME(mc) {
555
// padding
556
uchar
: 4;
558
uchar
emergency_routing
: 2;
559
// padding
560
uchar
: 2;
561
}
mc
;
563
struct
DOXYNAME(p2p) {
564
// padding
565
uchar
: 4;
567
uchar
seq_code
: 2;
568
// padding
569
uchar
: 2;
570
}
p2p
;
572
struct
DOXYNAME(nn) {
573
// padding
574
uchar
: 2;
576
uchar
route
: 3;
578
uchar
mem_or_normal
: 1;
579
// padding
580
uchar
: 2;
581
}
nn
;
583
struct
DOXYNAME(fr) {
584
// padding
585
uchar
: 4;
587
uchar
emergency_routing
: 2;
588
// padding
589
uchar
: 2;
590
}
fr
;
591
uchar
value;
592
}
spinnaker_packet_control_byte_t
;
593
595
enum
spinnaker_packet_type_t
{
597
SPINNAKER_PACKET_TYPE_MC
= 0,
599
SPINNAKER_PACKET_TYPE_P2P
= 1,
601
SPINNAKER_PACKET_TYPE_NN
= 2,
603
SPINNAKER_PACKET_TYPE_FR
= 3,
604
};
605
607
typedef
struct
{
608
// padding
609
uint
: 16;
611
uint
control_byte
: 8;
612
// padding
613
uint
: 4;
615
uint
not_full
: 1;
617
uint
overrun
: 1;
619
uint
full
: 1;
621
uint
empty
: 1;
622
}
comms_tx_control_t
;
623
625
typedef
struct
{
627
uint
multicast
: 1;
629
uint
point_to_point
: 1;
631
uint
nearest_neighbour
: 1;
633
uint
fixed_route
: 1;
634
// padding
635
uint
: 12;
637
uint
control_byte
: 8;
639
uint
route
: 3;
640
// padding
641
uint
: 1;
643
uint
error_free
: 1;
645
uint
framing_error
: 1;
647
uint
parity_error
: 1;
649
uint
received
: 1;
650
}
comms_rx_status_t
;
651
653
typedef
struct
{
655
uint
p2p_source_id
: 16;
656
// padding
657
uint
: 8;
659
uint
route
: 3;
660
// padding
661
uint
: 5;
662
}
comms_source_addr_t
;
663
665
typedef
struct
{
667
comms_tx_control_t
tx_control
;
669
uint
tx_data
;
671
uint
tx_key
;
673
comms_rx_status_t
rx_status
;
675
const
uint
rx_data
;
678
const
uint
rx_key
;
680
comms_source_addr_t
source_addr
;
682
const
uint
_test;
683
}
comms_ctl_t
;
684
685
ASSERT_WORD_SIZED
(
comms_tx_control_t
);
686
ASSERT_WORD_SIZED
(
comms_rx_status_t
);
687
ASSERT_WORD_SIZED
(
comms_source_addr_t
);
688
690
static
volatile
comms_ctl_t
*
const
comms_control
= (
comms_ctl_t
*) CC_BASE;
691
693
694
// ---------------------------------------------------------------------
695
// 9. Communications NoC
696
697
// No registers
698
699
// ---------------------------------------------------------------------
715
717
typedef
struct
{
719
uint
route_packets_enable
: 1;
721
uint
error_interrupt_enable
: 1;
723
uint
dump_interrupt_enable
: 1;
725
uint
count_timestamp_errors
: 1;
727
uint
count_framing_errors
: 1;
729
uint
count_parity_errors
: 1;
731
uint
time_phase
: 2;
733
uint
monitor_processor
: 5;
734
// padding
735
uint
: 2;
737
uint
reinit_wait_counters
: 1;
739
uint
begin_emergency_wait_time
: 8;
741
uint
drop_wait_time
: 8;
742
}
router_control_t
;
743
745
typedef
struct
{
747
uint
interrupt_active_for_diagnostic_counter
: 16;
749
uint
busy
: 1;
750
// padding
751
uint
: 7;
753
uint
output_stage
: 2;
754
// padding
755
uint
: 3;
757
uint
interrupt_active_dump
: 1;
759
uint
interrupt_active_error
: 1;
761
uint
interrupt_active
: 1;
762
}
router_status_t
;
763
765
enum
router_output_stage
{
767
ROUTER_OUTPUT_STAGE_EMPTY
,
769
ROUTER_OUTPUT_STAGE_FULL
,
771
ROUTER_OUTPUT_STAGE_WAIT1
,
773
ROUTER_OUTPUT_STAGE_WAIT2
774
};
775
777
typedef
union
{
779
struct
DOXYNAME(flags) {
780
// padding
781
uint
: 6;
783
uint
time_phase
: 2;
784
// padding
785
uint
: 8;
787
uint
control
: 8;
789
uint
route
: 3;
791
uint
time_phase_error
: 1;
793
uint
framing_error
: 1;
795
uint
parity_error
: 1;
796
// padding
797
uint
: 2;
798
};
800
struct
DOXYNAME(control_field_bits) {
801
// padding
802
uint
: 17;
804
uint
payload
: 1;
805
// padding
806
uint
: 4;
808
uint
type
: 2;
809
};
811
uint
word
;
812
}
router_packet_header_t
;
813
815
typedef
struct
{
817
uint
error_count
: 16;
818
// padding
819
uint
: 11;
821
uint
time_phase_error
: 1;
823
uint
framing_error
: 1;
825
uint
parity_error
: 1;
827
uint
overflow
: 1;
829
uint
error
: 1;
830
}
router_error_status_t
;
831
833
typedef
struct
{
835
uint
link
:
NUM_LINKS
;
837
uint
processor
:
NUM_CPUS
;
838
// padding
839
uint
: 8;
840
}
router_dump_outputs_t
;
841
843
typedef
struct
{
845
uint
link
:
NUM_LINKS
;
847
uint
processor
:
NUM_CPUS
;
848
// padding
849
uint
: 6;
851
uint
overflow
: 1;
853
uint
dumped
: 1;
854
}
router_dump_status_t
;
855
857
typedef
struct
{
859
ushort
enable
;
861
ushort
reset
;
862
}
router_diagnostic_counter_ctrl_t
;
863
865
typedef
struct
{
867
uint
enable_cycle_count
: 1;
869
uint
enable_emergency_active_count
: 1;
871
uint
enable_histogram
: 1;
872
// padding
873
uint
: 13;
875
uint
reset_cycle_count
: 1;
877
uint
reset_emergency_active_count
: 1;
879
uint
reset_histogram
: 1;
880
// padding
881
uint
: 13;
882
}
router_timing_counter_ctrl_t
;
883
885
typedef
struct
{
887
uint
L0
: 2;
889
uint
L1
: 2;
891
uint
L2
: 2;
893
uint
L3
: 2;
895
uint
L4
: 2;
897
uint
L5
: 2;
898
// padding
899
uint
: 20;
900
}
router_diversion_t
;
901
903
enum
router_diversion_rule_t
{
905
ROUTER_DIVERSION_NORMAL
,
907
ROUTER_DIVERSION_MONITOR
,
909
ROUTER_DIVERSION_DESTROY
910
};
911
913
typedef
struct
{
915
uint
fr_links
:
NUM_LINKS
;
917
uint
fr_processors
:
NUM_CPUS
;
918
// padding
919
uint
: 2;
921
uint
nn_broadcast_links
:
NUM_LINKS
;
922
}
router_fixed_route_routing_t
;
923
925
typedef
struct
{
927
router_control_t
control
;
929
const
router_status_t
status
;
931
struct
DOXYNAME(error) {
933
const
router_packet_header_t
header
;
935
const
uint
key
;
937
const
uint
payload
;
939
const
router_error_status_t
status
;
940
}
error
;
942
struct
DOXYNAME(dump) {
944
const
router_packet_header_t
header
;
946
const
uint
key
;
948
const
uint
payload
;
950
const
router_dump_outputs_t
outputs
;
952
const
router_dump_status_t
status
;
953
}
dump
;
955
router_diagnostic_counter_ctrl_t
diagnostic_counter_control
;
957
router_timing_counter_ctrl_t
timing_counter_control
;
959
const
uint
cycle_count
;
961
const
uint
emergency_active_cycle_count
;
963
const
uint
unblocked_count
;
965
const
uint
delay_histogram[16];
967
router_diversion_t
diversion
;
969
router_fixed_route_routing_t
fixed_route
;
970
}
router_t
;
971
973
typedef
struct
{
975
uint
type
: 4;
977
uint
emergency_routing
: 4;
979
uint
emergency_routing_mode
: 1;
980
// padding
981
uint
: 1;
983
uint
pattern_default
: 2;
985
uint
pattern_payload
: 2;
987
uint
pattern_local
: 2;
989
uint
pattern_destination
: 9;
990
// padding
991
uint
: 4;
993
uint
counter_event_occurred
: 1;
995
uint
enable_counter_event_interrupt
: 1;
997
uint
counter_event_interrupt_active
: 1;
998
}
router_diagnostic_filter_t
;
999
1001
typedef
union
{
1003
struct
DOXYNAME(routes) {
1005
uint
links
:
NUM_LINKS
;
1007
uint
processors
:
NUM_CPUS
;
1008
};
1010
uint
value
;
1011
}
router_multicast_route_t
;
1012
1014
typedef
enum
{
1016
ROUTER_P2P_ROUTE_E
,
1018
ROUTER_P2P_ROUTE_NE
,
1020
ROUTER_P2P_ROUTE_N
,
1022
ROUTER_P2P_ROUTE_W
,
1024
ROUTER_P2P_ROUTE_SW
,
1026
ROUTER_P2P_ROUTE_S
,
1028
ROUTER_P2P_ROUTE_DROP
,
1031
ROUTER_P2P_ROUTE_MONITOR
1032
}
router_p2p_route
;
1033
1035
typedef
union
{
1037
struct
DOXYNAME(routes) {
1039
router_p2p_route
route1
: 3;
1041
router_p2p_route
route2
: 3;
1043
router_p2p_route
route3
: 3;
1045
router_p2p_route
route4
: 3;
1047
router_p2p_route
route5
: 3;
1049
router_p2p_route
route6
: 3;
1051
router_p2p_route
route7
: 3;
1053
router_p2p_route
route8
: 3;
1054
};
1056
uint
value
;
1057
}
router_p2p_table_entry_t
;
1058
1059
ASSERT_WORD_SIZED
(
router_control_t
);
1060
ASSERT_WORD_SIZED
(
router_packet_header_t
);
1061
ASSERT_WORD_SIZED
(
router_error_status_t
);
1062
ASSERT_WORD_SIZED
(
router_dump_outputs_t
);
1063
ASSERT_WORD_SIZED
(
router_dump_status_t
);
1064
ASSERT_WORD_SIZED
(
router_diagnostic_counter_ctrl_t
);
1065
ASSERT_WORD_SIZED
(
router_timing_counter_ctrl_t
);
1066
ASSERT_WORD_SIZED
(
router_diversion_t
);
1067
ASSERT_WORD_SIZED
(
router_fixed_route_routing_t
);
1068
ASSERT_WORD_SIZED
(
router_diagnostic_filter_t
);
1069
ASSERT_WORD_SIZED
(
router_multicast_route_t
);
1070
ASSERT_WORD_SIZED
(
router_p2p_table_entry_t
);
1071
1073
static
volatile
router_t
*
const
router_control
= (
router_t
*) RTR_BASE;
1075
static
volatile
router_diagnostic_filter_t
*
const
router_diagnostic_filter
=
1076
(
router_diagnostic_filter_t
*) (RTR_BASE + 0x200);
1078
static
volatile
uint
*
const
router_diagnostic_counter
=
1079
(
uint
*) (RTR_BASE + 0x300);
1081
static
volatile
router_multicast_route_t
*
const
router_multicast_table
=
1082
(
router_multicast_route_t
*) RTR_MCRAM_BASE;
1084
static
volatile
uint
*
const
router_key_table
= (
uint
*) RTR_MCKEY_BASE;
1086
static
volatile
uint
*
const
router_mask_table
= (
uint
*) RTR_MCMASK_BASE;
1088
static
volatile
router_p2p_table_entry_t
*
const
router_p2p_route_table
=
1089
(
router_p2p_table_entry_t
*) RTR_P2P_BASE;
1090
1092
1093
// ---------------------------------------------------------------------
1094
// 11. Inter-chip transmit and receive interfaces
1095
1096
// No registers
1097
1098
// ---------------------------------------------------------------------
1099
// 12. System NoC
1100
1101
// No registers
1102
1103
// ---------------------------------------------------------------------
1111
1113
typedef
struct
{
1115
uint
status
: 2;
1117
uint
width
: 2;
1119
uint
ddr
: 3;
1121
uint
chips
: 2;
1123
uint
banks
: 1;
1125
uint
monitors
: 2;
1126
// padding
1127
uint
: 20;
1128
}
sdram_status_t
;
1129
1131
typedef
struct
{
1133
uint
command
: 3;
1134
}
sdram_command_t
;
1135
1138
enum
sdram_command
{
1140
SDRAM_CTL_GO
,
1142
SDRAM_CTL_SLEEP
,
1144
SDRAM_CTL_WAKE
,
1146
SDRAM_CTL_PAUSE
,
1148
SDRAM_CTL_CONFIG
,
1150
SDRAM_CTL_ACTIVE_PAUSE
1151
};
1152
1156
typedef
struct
{
1158
uint
address
: 14;
1159
// padding
1160
uint
: 2;
1162
uint
bank
: 2;
1164
uint
cmd
: 2;
1166
uint
chip
: 2;
1167
// padding
1168
uint
: 10;
1169
}
sdram_direct_command_t
;
1170
1173
enum
sdram_direct_command
{
1175
SDRAM_DIRECT_PRECHARGE
= 0,
1177
SDRAM_DIRECT_AUTOREFRESH
= 1,
1179
SDRAM_DIRECT_MODEREG
= 2,
1181
SDRAM_DIRECT_NOP
= 3,
1182
};
1183
1185
typedef
struct
{
1187
uint
column
: 3;
1189
uint
row
: 3;
1191
uint
auto_precharge_position
: 1;
1193
uint
power_down_delay
: 6;
1195
uint
auto_power_down
: 1;
1197
uint
stop_clock
: 1;
1199
uint
burst
: 3;
1201
uint
qos
: 3;
1203
uint
active
: 2;
1204
// padding
1205
uint
: 9;
1206
}
sdram_ram_config_t
;
1207
1209
typedef
struct
{
1211
uint
period
: 15;
1212
// padding
1213
uint
: 17;
1214
}
sdram_refresh_t
;
1215
1217
typedef
struct
{
1219
uint
half_cycle
: 1;
1221
uint
cas_lat
: 3;
1222
// padding
1223
uint
: 28;
1224
}
sdram_cas_latency_t
;
1225
1228
typedef
struct
{
1230
uint
t_dqss
;
1232
uint
t_mrd
;
1234
uint
t_ras
;
1236
uint
t_rc
;
1238
uint
t_rcd
;
1240
uint
t_rfc
;
1242
uint
t_rp
;
1244
uint
t_rrd
;
1246
uint
t_wr
;
1248
uint
t_wtr
;
1250
uint
t_xp
;
1252
uint
t_xsr
;
1254
uint
t_esr
;
1255
}
sdram_timing_config_t
;
1256
1258
typedef
struct
{
1260
const
sdram_status_t
status
;
1262
sdram_command_t
command
;
1264
sdram_direct_command_t
direct
;
1266
sdram_ram_config_t
mem_config
;
1268
sdram_refresh_t
refresh
;
1270
sdram_cas_latency_t
cas_latency
;
1272
sdram_timing_config_t
timing_config
;
1273
}
sdram_controller_t
;
1274
1276
typedef
struct
{
1278
uint
enable
: 1;
1280
uint
minimum
: 1;
1282
uint
maximum
: 8;
1283
// padding
1284
uint
: 22;
1285
}
sdram_qos_t
;
1286
1288
typedef
struct
{
1290
uint
mask
: 8;
1292
uint
match
: 8;
1294
uint
orientation
: 1;
1295
// padding
1296
uint
: 15;
1297
}
sdram_chip_t
;
1298
1300
enum
sdram_register_maxima
{
1302
SDRAM_QOS_MAX
= 15,
1304
SDRAM_CHIP_MAX
= 3
1305
};
1306
1308
typedef
struct
{
1310
uint
meter
: 7;
1311
// padding
1312
uint
: 1;
1314
uint
s0
: 1;
1316
uint
c0
: 1;
1318
uint
s1
: 1;
1320
uint
c1
: 1;
1322
uint
s2
: 1;
1324
uint
c2
: 1;
1326
uint
s3
: 1;
1328
uint
c3
: 1;
1330
uint
decing
: 1;
1332
uint
incing
: 1;
1334
uint
locked
: 1;
1335
// padding
1336
uint
: 1;
1338
uint
R
: 1;
1340
uint
M
: 1;
1342
uint
L
: 1;
1343
// padding
1344
uint
: 9;
1345
}
sdram_dll_status_t
;
1346
1348
typedef
struct
{
1350
uint
s0
: 2;
1352
uint
s1
: 2;
1354
uint
s2
: 2;
1356
uint
s3
: 2;
1358
uint
s4
: 2;
1360
uint
s5
: 2;
1361
// padding
1362
uint
: 4;
1364
uint
test_decing
: 1;
1366
uint
test_incing
: 1;
1368
uint
enable_force_inc_dec
: 1;
1370
uint
test_5
: 1;
1372
uint
R
: 1;
1374
uint
M
: 1;
1376
uint
L
: 1;
1378
uint
enable_force_lmr
: 1;
1380
uint
enable
: 1;
1381
// padding
1382
uint
: 7;
1383
}
sdram_dll_user_config0_t
;
1384
1386
typedef
union
{
1388
struct
DOXYNAME(tuning) {
1390
uint
tune_0
: 4;
1392
uint
tune_1
: 4;
1394
uint
tune_2
: 4;
1396
uint
tune_3
: 4;
1398
uint
tune_4
: 4;
1400
uint
tune_5
: 4;
1401
// padding
1402
uint
: 8;
1403
};
1405
uint
word
;
1406
}
sdram_dll_user_config1_t
;
1407
1409
typedef
struct
{
1411
const
sdram_dll_status_t
status
;
1413
sdram_dll_user_config0_t
config0
;
1415
sdram_dll_user_config1_t
config1
;
1416
}
sdram_dll_t
;
1417
1418
ASSERT_WORD_SIZED
(
sdram_status_t
);
1419
ASSERT_WORD_SIZED
(
sdram_command_t
);
1420
ASSERT_WORD_SIZED
(
sdram_direct_command_t
);
1421
ASSERT_WORD_SIZED
(
sdram_ram_config_t
);
1422
ASSERT_WORD_SIZED
(
sdram_refresh_t
);
1423
ASSERT_WORD_SIZED
(
sdram_cas_latency_t
);
1424
ASSERT_WORD_SIZED
(
sdram_qos_t
);
1425
ASSERT_WORD_SIZED
(
sdram_chip_t
);
1426
ASSERT_WORD_SIZED
(
sdram_dll_status_t
);
1427
ASSERT_WORD_SIZED
(
sdram_dll_user_config0_t
);
1428
ASSERT_WORD_SIZED
(
sdram_dll_user_config1_t
);
1429
1431
static
volatile
sdram_controller_t
*
const
sdram_control
=
1432
(
sdram_controller_t
*) PL340_BASE;
1434
static
volatile
sdram_qos_t
*
const
sdram_qos_control
=
1435
(
sdram_qos_t
*) (PL340_BASE + 0x100);
1437
static
volatile
sdram_chip_t
*
const
sdram_chip_control
=
1438
(
sdram_chip_t
*) (PL340_BASE + 0x200);
1440
static
volatile
sdram_dll_t
*
const
sdram_dll_control
=
1441
(
sdram_dll_t
*) (PL340_BASE + 0x300);
1442
1444
1445
// ---------------------------------------------------------------------
1462
1464
typedef
struct
{
1466
uint
select
:
NUM_CPUS
;
1467
// padding
1468
uint
: 2;
1470
uint
security_code
: 12;
1471
}
sc_magic_proc_map_t
;
1472
1474
typedef
struct
{
1476
uint
router
: 1;
1478
uint
sdram
: 1;
1480
uint
system_noc
: 1;
1482
uint
comms_noc
: 1;
1484
uint
tx_links
:
NUM_LINKS
;
1486
uint
rx_links
:
NUM_LINKS
;
1488
uint
clock_gen
: 1;
1490
uint
entire_chip
: 1;
1491
// padding
1492
uint
: 2;
1494
uint
security_code
: 12;
1495
}
sc_magic_subsystem_map_t
;
1496
1498
typedef
struct
{
1500
uint
reset_code
: 3;
1501
// padding
1502
uint
: 29;
1503
}
sc_reset_code_t
;
1504
1506
enum
sc_reset_codes
{
1508
SC_RESET_CODE_POR
,
1510
SC_RESET_CODE_WDR
,
1512
SC_RESET_CODE_UR
,
1514
SC_RESET_CODE_REC
,
1516
SC_RESET_CODE_WDI
1517
};
1518
1520
typedef
struct
{
1522
uint
monitor_id
: 5;
1523
// padding
1524
uint
: 3;
1526
uint
arbitrate_request
: 1;
1527
// padding
1528
uint
: 7;
1530
uint
reset_on_watchdog
: 1;
1531
// padding
1532
uint
: 3;
1534
uint
security_code
: 12;
1535
}
sc_monitor_id_t
;
1536
1538
typedef
struct
{
1540
uint
boot_area_map
: 1;
1541
// padding
1542
uint
: 14;
1544
uint
jtag_on_chip
: 1;
1546
uint
test
: 1;
1548
uint
ethermux
: 1;
1550
uint
clk32
: 1;
1552
uint
jtag_tdo
: 1;
1554
uint
jtag_rtck
: 1;
1555
// padding
1556
uint
: 11;
1557
}
sc_misc_control_t
;
1558
1560
typedef
union
{
1562
struct
DOXYNAME(io_bits) {
1563
// padding
1564
uint
: 16;
1566
uint
ethernet_receive
: 4;
1568
uint
ethernet_transmit
: 4;
1570
uint
jtag
: 4;
1571
// padding
1572
uint
: 1;
1574
uint
sdram
: 3;
1575
};
1577
uint
gpio
;
1578
}
sc_io_t
;
1579
1581
typedef
struct
{
1583
uint
input_multiplier
: 6;
1584
// padding
1585
uint
: 2;
1587
uint
output_divider
: 6;
1588
// padding
1589
uint
: 2;
1591
uint
freq_range
: 2;
1593
uint
power_up
: 1;
1594
// padding
1595
uint
: 5;
1597
uint
_test : 1;
1598
// padding
1599
uint
: 7;
1600
}
sc_pll_control_t
;
1601
1603
enum
sc_frequency_range
{
1605
FREQ_25_50
,
1607
FREQ_50_100
,
1609
FREQ_100_200
,
1611
FREQ_200_400
1612
};
1613
1615
typedef
struct
{
1617
uint
pa
: 2;
1619
uint
adiv
: 2;
1620
// padding
1621
uint
: 1;
1623
uint
pb
: 2;
1625
uint
bdiv
: 2;
1626
// padding
1627
uint
: 1;
1629
uint
mem
: 2;
1631
uint
mdiv
: 2;
1632
// padding
1633
uint
: 1;
1635
uint
rtr
: 2;
1637
uint
rdiv
: 2;
1638
// padding
1639
uint
: 1;
1641
uint
sys
: 2;
1643
uint
sdiv
: 2;
1644
// padding
1645
uint
: 7;
1647
uint
invert_b
: 1;
1648
}
sc_clock_mux_t
;
1649
1653
enum
sc_clock_source
{
1655
CLOCK_SRC_EXT
,
1657
CLOCK_SRC_PLL1
,
1659
CLOCK_SRC_PLL2
,
1661
CLOCK_SRC_EXT4
1662
};
1663
1665
typedef
struct
{
1667
uint
status
:
NUM_CPUS
;
1668
// padding
1669
uint
: 14;
1670
}
sc_sleep_status_t
;
1671
1673
typedef
struct
{
1675
uint
temperature
: 24;
1677
uint
sample_finished
: 1;
1678
// padding
1679
uint
: 6;
1681
uint
start
: 1;
1682
}
sc_temperature_t
;
1683
1685
typedef
struct
{
1686
// padding
1687
uint
: 31;
1689
uint
bit
: 1;
1690
}
sc_mutex_bit_t
;
1691
1693
typedef
struct
{
1695
uint
rx_disable
:
NUM_LINKS
;
1696
// padding
1697
uint
: 2;
1699
uint
tx_disable
:
NUM_LINKS
;
1700
// padding
1701
uint
: 2;
1703
uint
parity_control
: 1;
1704
// padding
1705
uint
: 3;
1707
uint
security_code
: 12;
1708
}
sc_link_disable_t
;
1709
1710
#define _NUM_TEMPS 3
1711
#define _NUM_ARBITERS 32
1712
#define _NUM_LOCK_REGISTERS 32
1713
1715
typedef
struct
{
1717
const
uint
chip_id
;
1719
sc_magic_proc_map_t
processor_disable
;
1721
sc_magic_proc_map_t
set_cpu_irq
;
1723
sc_magic_proc_map_t
clear_cpu_irq
;
1725
uint
set_cpu_ok
;
1727
uint
clear_cpu_ok
;
1729
sc_magic_proc_map_t
cpu_soft_reset_level
;
1731
sc_magic_proc_map_t
cpu_hard_reset_level
;
1733
sc_magic_subsystem_map_t
subsystem_reset_level
;
1735
sc_magic_proc_map_t
cpu_soft_reset_pulse
;
1737
sc_magic_proc_map_t
cpu_hard_reset_pulse
;
1739
sc_magic_subsystem_map_t
subsystem_reset_pulse
;
1741
const
sc_reset_code_t
reset_code
;
1743
sc_monitor_id_t
monitor_id
;
1745
sc_misc_control_t
misc_control
;
1747
sc_io_t
gpio_pull_up_down_enable
;
1749
sc_io_t
io_port
;
1751
sc_io_t
io_direction
;
1753
sc_io_t
io_set
;
1755
sc_io_t
io_clear
;
1757
sc_pll_control_t
pll1_freq_control
;
1759
sc_pll_control_t
pll2_freq_control
;
1761
uint
set_flags
;
1763
uint
reset_flags
;
1765
sc_clock_mux_t
clock_mux_control
;
1767
const
sc_sleep_status_t
cpu_sleep
;
1769
sc_temperature_t
temperature[_NUM_TEMPS];
1770
// padding
1771
const
uint
_padding[3];
1773
const
sc_mutex_bit_t
monitor_arbiter[_NUM_ARBITERS];
1775
const
sc_mutex_bit_t
test_and_set[_NUM_LOCK_REGISTERS];
1777
const
sc_mutex_bit_t
test_and_clear[_NUM_LOCK_REGISTERS];
1779
sc_link_disable_t
link_disable
;
1780
}
system_controller_t
;
1781
1783
enum
sc_magic
{
1785
SYSTEM_CONTROLLER_MAGIC_NUMBER
= 0x5ec
1786
};
1787
1788
ASSERT_WORD_SIZED
(
sc_magic_proc_map_t
);
1789
ASSERT_WORD_SIZED
(
sc_reset_code_t
);
1790
ASSERT_WORD_SIZED
(
sc_monitor_id_t
);
1791
ASSERT_WORD_SIZED
(
sc_misc_control_t
);
1792
ASSERT_WORD_SIZED
(
sc_io_t
);
1793
ASSERT_WORD_SIZED
(
sc_pll_control_t
);
1794
ASSERT_WORD_SIZED
(
sc_clock_mux_t
);
1795
ASSERT_WORD_SIZED
(
sc_sleep_status_t
);
1796
ASSERT_WORD_SIZED
(
sc_temperature_t
);
1797
ASSERT_WORD_SIZED
(
sc_mutex_bit_t
);
1798
ASSERT_WORD_SIZED
(
sc_link_disable_t
);
1799
1801
static
volatile
system_controller_t
*
const
system_control
=
1802
(
system_controller_t
*) SYSCTL_BASE;
1803
1805
1806
// ---------------------------------------------------------------------
1816
1818
typedef
struct
{
1820
uint
transmit
: 1;
1822
uint
receive
: 1;
1824
uint
loopback
: 1;
1826
uint
receive_error_filter
: 1;
1828
uint
receive_unicast
: 1;
1830
uint
receive_multicast
: 1;
1832
uint
receive_broadcast
: 1;
1834
uint
receive_promiscuous
: 1;
1836
uint
receive_vlan
: 1;
1838
uint
reset_drop_counter
: 1;
1840
uint
hardware_byte_reorder_disable
: 1;
1841
// padding
1842
uint
: 21;
1843
}
ethernet_general_command_t
;
1844
1846
typedef
struct
{
1848
uint
transmit_active
: 1;
1850
uint
unread_counter
: 6;
1851
// padding
1852
uint
: 9;
1854
uint
drop_counter
: 16;
1855
}
ethernet_general_status_t
;
1856
1858
typedef
struct
{
1860
uint
tx_length
: 11;
1861
}
ethernet_tx_length_t
;
1862
1864
enum
ethernet_tx_length_limits
{
1866
ETHERNET_TX_LENGTH_MIN
= 60,
1868
ETHERNET_TX_LENGTH_MAX
= 1514
1869
};
1870
1872
typedef
struct
{
1874
uint
reset
: 1;
1876
uint
smi_input
: 1;
1878
uint
smi_output
: 1;
1880
uint
smi_out_enable
: 1;
1882
uint
smi_clock
: 1;
1884
uint
irq_invert_disable
: 1;
1885
// padding
1886
uint
: 26;
1887
}
ethernet_phy_control_t
;
1888
1890
typedef
struct
{
1892
uint
transmit
: 1;
1893
// padding
1894
uint
: 3;
1896
uint
receive
: 1;
1897
// padding
1898
uint
: 27;
1899
}
ethernet_interrupt_clear_t
;
1900
1902
typedef
struct
{
1904
uint
ptr
: 12;
1906
uint
rollover
: 1;
1907
// padding
1908
uint
: 19;
1909
}
ethernet_receive_pointer_t
;
1910
1912
typedef
struct
{
1914
uint
ptr
: 6;
1916
uint
rollover
: 1;
1917
// padding
1918
uint
: 25;
1919
}
ethernet_receive_descriptor_pointer_t
;
1920
1922
typedef
struct
{
1924
ethernet_general_command_t
command
;
1926
const
ethernet_general_status_t
status
;
1928
ethernet_tx_length_t
transmit_length
;
1930
uint
transmit_command
;
1932
uint
receive_command
;
1934
uint64
mac_address
;
1936
ethernet_phy_control_t
phy_control
;
1938
ethernet_interrupt_clear_t
interrupt_clear
;
1940
const
ethernet_receive_pointer_t
receive_read
;
1942
const
ethernet_receive_pointer_t
receive_write
;
1944
const
ethernet_receive_descriptor_pointer_t
receive_desc_read
;
1946
const
ethernet_receive_descriptor_pointer_t
receive_desc_write
;
1948
uint
_test[3];
1949
}
ethernet_controller_t
;
1950
1954
typedef
struct
{
1956
uint
length
: 11;
1957
// unknown; might be padding or status bits?
1958
uint
: 21;
1959
}
ethernet_receive_descriptor_t
;
1960
1961
ASSERT_WORD_SIZED
(
ethernet_general_command_t
);
1962
ASSERT_WORD_SIZED
(
ethernet_general_status_t
);
1963
ASSERT_WORD_SIZED
(
ethernet_tx_length_t
);
1964
ASSERT_WORD_SIZED
(
ethernet_phy_control_t
);
1965
ASSERT_WORD_SIZED
(
ethernet_interrupt_clear_t
);
1966
ASSERT_WORD_SIZED
(
ethernet_receive_pointer_t
);
1967
ASSERT_WORD_SIZED
(
ethernet_receive_descriptor_pointer_t
);
1968
ASSERT_WORD_SIZED
(
ethernet_receive_descriptor_t
);
1969
1971
static
volatile
uchar
*
const
ethernet_tx_buffer
= (
uchar
*) ETH_TX_BASE;
1973
static
volatile
uchar
*
const
ethernet_rx_buffer
= (
uchar
*) ETH_RX_BASE;
1975
static
volatile
ethernet_receive_descriptor_t
*
const
ethernet_desc_buffer
=
1976
(
ethernet_receive_descriptor_t
*) ETH_RX_DESC_RAM;
1978
static
volatile
ethernet_controller_t
*
const
ethernet_control
=
1979
(
ethernet_controller_t
*) ETH_REGS;
1980
1982
1983
// ---------------------------------------------------------------------
1993
1995
typedef
struct
{
1997
uint
interrupt_enable
: 1;
1999
uint
reset_enable
: 1;
2000
// padding
2001
uint
: 30;
2002
}
watchdog_control_t
;
2003
2005
typedef
struct
{
2007
uint
interrupted
: 1;
2008
// padding
2009
uint
: 31;
2010
}
watchdog_status_t
;
2011
2013
typedef
union
{
2015
struct
DOXYNAME(fields) {
2017
uint
lock
: 1;
2019
uint
magic
: 31;
2020
};
2022
uint
whole_value
;
2023
}
watchdog_lock_t
;
2024
2026
enum
watchdog_lock_codes
{
2028
WATCHDOG_LOCK_RESET
= 0,
2030
WATCHDOG_LOCK_MAGIC
=
WD_CODE
2031
};
2032
2034
typedef
struct
{
2036
uint
load
;
2038
const
uint
value
;
2040
watchdog_control_t
control
;
2042
uint
interrupt_clear
;
2044
const
watchdog_status_t
raw_status
;
2046
const
watchdog_status_t
masked_status
;
2047
// Lots of padding!
2048
const
uint
_padding[0x2fa];
2050
watchdog_lock_t
lock
;
2051
}
watchdog_controller_t
;
2052
2053
ASSERT_WORD_SIZED
(
watchdog_control_t
);
2054
ASSERT_WORD_SIZED
(
watchdog_status_t
);
2055
ASSERT_WORD_SIZED
(
watchdog_lock_t
);
2056
2058
static
volatile
watchdog_controller_t
*
const
watchdog_control
=
2059
(
watchdog_controller_t
*) WDOG_BASE;
2060
2062
2063
// ---------------------------------------------------------------------
2064
// 17. System RAM
2065
2066
// No registers
2067
2068
// ---------------------------------------------------------------------
2069
// 18. Boot ROM
2070
2071
// No registers
2072
2073
// ---------------------------------------------------------------------
2074
// 19. JTAG
2075
2076
// No registers
2077
2078
// ---------------------------------------------------------------------
2079
// 20. Input and Output Signals
2080
2081
// No registers
2082
2083
// ---------------------------------------------------------------------
2084
// 21. Packaging
2085
2086
// No registers
2087
2088
// ---------------------------------------------------------------------
2089
// 22. Application Notes
2090
2091
// No registers
2092
2093
// ---------------------------------------------------------------------
2094
#endif
// !__SPINN_EXTRA_H__
ethernet_general_command_t::reset_drop_counter
uint reset_drop_counter
Reset receive dropped frame count (ethernet_general_status_t::drop_counter)
Definition
spinn_extra.h:1838
router_multicast_table
static volatile router_multicast_route_t *const router_multicast_table
Router multicast route table.
Definition
spinn_extra.h:1081
router_t::control
router_control_t control
Router control register.
Definition
spinn_extra.h:927
comms_rx_status_t::nearest_neighbour
uint nearest_neighbour
error-free nearest-neighbour packet received
Definition
spinn_extra.h:631
ethernet_general_command_t::receive_vlan
uint receive_vlan
Receive VLAN enable.
Definition
spinn_extra.h:1836
router_diversion_t::L2
uint L2
Diversion rule for link 2.
Definition
spinn_extra.h:891
sdram_dll_user_config0_t::s4
uint s4
Input select for delay line 4 {def, alt, 0, 1}.
Definition
spinn_extra.h:1358
dma_t::statistics_control
dma_stats_control_t statistics_control
Statistics counters control.
Definition
spinn_extra.h:500
system_controller_t::set_flags
uint set_flags
Set flags register.
Definition
spinn_extra.h:1761
vic_mask_t::interrupt_bits::cc_rx_fr
uint cc_rx_fr
Comms controller fixed route packet received.
Definition
spinn_extra.h:163
dma_control_t::clear_write_buffer_int
uint clear_write_buffer_int
clear Write Buffer interrupt request
Definition
spinn_extra.h:380
ethernet_general_command_t::loopback
uint loopback
Loopback enable.
Definition
spinn_extra.h:1824
watchdog_controller_t::load
uint load
Count load register.
Definition
spinn_extra.h:2036
sdram_dll_status_t::R
uint R
3-phase bar-code control output
Definition
spinn_extra.h:1338
sc_clock_mux_t::pb
uint pb
clock selector for B CPUs (0 3 5 6 9 10 12 15 17); see sc_clock_source
Definition
spinn_extra.h:1623
ethernet_controller_t::transmit_command
uint transmit_command
Transmit command; any value commits transmit.
Definition
spinn_extra.h:1930
sdram_dll_status_t::c1
uint c1
Clock faster than strobe 1.
Definition
spinn_extra.h:1320
watchdog_lock_t::fields::magic
uint magic
Access control code.
Definition
spinn_extra.h:2019
dma_timeout_t::value
uint value
The timeout.
Definition
spinn_extra.h:462
sdram_chip_t::mask
uint mask
address mask
Definition
spinn_extra.h:1290
timer_controller_t::current_value
const uint current_value
Current value of Timer.
Definition
spinn_extra.h:286
router_dump_status_t::dumped
uint dumped
packet dumped
Definition
spinn_extra.h:853
system_control
static volatile system_controller_t *const system_control
System controller registers.
Definition
spinn_extra.h:1801
router_diversion_t::L4
uint L4
Diversion rule for link 4.
Definition
spinn_extra.h:895
sc_io_t::io_bits::ethernet_receive
uint ethernet_receive
Ethernet MII RxD port.
Definition
spinn_extra.h:1566
vic_mask_t::interrupt_bits::gpio8
uint gpio8
Signal on GPIO[8].
Definition
spinn_extra.h:169
ethernet_tx_length_limits
ethernet_tx_length_limits
Limits of ethernet_tx_length_t::tx_length.
Definition
spinn_extra.h:1864
ETHERNET_TX_LENGTH_MIN
@ ETHERNET_TX_LENGTH_MIN
Minimum length of an ethernet frame.
Definition
spinn_extra.h:1866
ETHERNET_TX_LENGTH_MAX
@ ETHERNET_TX_LENGTH_MAX
Maximum length of an ethernet frame.
Definition
spinn_extra.h:1868
router_t::dump::status
const router_dump_status_t status
dumped packet status
Definition
spinn_extra.h:952
system_controller_t::io_direction
sc_io_t io_direction
External I/O pin is input (1) or output (0)
Definition
spinn_extra.h:1751
router_control_t::dump_interrupt_enable
uint dump_interrupt_enable
enable dump packet interrupt
Definition
spinn_extra.h:723
router_p2p_table_entry_t::value
uint value
Overall entry packed as number.
Definition
spinn_extra.h:1056
router_t::fixed_route
router_fixed_route_routing_t fixed_route
fixed-route packet routing vector
Definition
spinn_extra.h:969
sc_magic_subsystem_map_t::router
uint router
Router.
Definition
spinn_extra.h:1476
watchdog_lock_t::fields::lock
uint lock
Write access enabled (0) or disabled (1)
Definition
spinn_extra.h:2017
watchdog_controller_t::lock
watchdog_lock_t lock
Lock register.
Definition
spinn_extra.h:2050
sc_clock_mux_t::mdiv
uint mdiv
divide SDRAM clock by Mdiv+1 (= 1-4)
Definition
spinn_extra.h:1631
router_status_t::interrupt_active_for_diagnostic_counter
uint interrupt_active_for_diagnostic_counter
diagnostic counter interrupt active
Definition
spinn_extra.h:747
sdram_dll_user_config0_t::enable_force_lmr
uint enable_force_lmr
Enable forcing of L, M, R.
Definition
spinn_extra.h:1378
router_p2p_table_entry_t::routes::route7
router_p2p_route route7
Seventh packed route.
Definition
spinn_extra.h:1051
system_controller_t::chip_id
const uint chip_id
Chip ID register (hardwired)
Definition
spinn_extra.h:1717
sdram_dll_status_t::L
uint L
3-phase bar-code control output
Definition
spinn_extra.h:1342
router_packet_header_t::control_field_bits::type
uint type
packet-type field from control byte
Definition
spinn_extra.h:808
sdram_dll_status_t::s2
uint s2
Strobe 2 faster than Clock.
Definition
spinn_extra.h:1322
watchdog_controller_t::control
watchdog_control_t control
Control register.
Definition
spinn_extra.h:2040
router_error_status_t::time_phase_error
uint time_phase_error
packet time stamp error (sticky)
Definition
spinn_extra.h:821
router_timing_counter_ctrl_t::enable_histogram
uint enable_histogram
enable histogram
Definition
spinn_extra.h:871
sc_monitor_id_t::security_code
uint security_code
SYSTEM_CONTROLLER_MAGIC_NUMBER to enable write
Definition
spinn_extra.h:1534
sdram_timing_config_t::t_xp
uint t_xp
exit power-down command time
Definition
spinn_extra.h:1250
router_error_status_t::parity_error
uint parity_error
packet parity error (sticky)
Definition
spinn_extra.h:825
vic_mask_t::interrupt_bits::cc_tx_not_full
uint cc_tx_not_full
Comms controller can accept new Tx packet.
Definition
spinn_extra.h:155
timer2_control
static volatile timer_controller_t *const timer2_control
Timer 2 control registers.
Definition
spinn_extra.h:308
router_status_t::output_stage
uint output_stage
Router output stage status (see router_output_stage)
Definition
spinn_extra.h:753
sdram_status_t::ddr
uint ddr
DDR type: 3b’011 = Mobile DDR.
Definition
spinn_extra.h:1119
system_controller_t::link_disable
sc_link_disable_t link_disable
Disables for Tx and Rx link interfaces.
Definition
spinn_extra.h:1779
sdram_dll_status_t::M
uint M
3-phase bar-code control output
Definition
spinn_extra.h:1340
router_status_t::interrupt_active_dump
uint interrupt_active_dump
dump packet interrupt active
Definition
spinn_extra.h:757
sc_misc_control_t::boot_area_map
uint boot_area_map
map System ROM (0) or RAM (1) to Boot area
Definition
spinn_extra.h:1540
ethernet_phy_control_t::reset
uint reset
PHY reset (active low)
Definition
spinn_extra.h:1874
timer_control_t::enable
uint enable
enable counter/timer (1 = enabled)
Definition
spinn_extra.h:258
timer_controller_t::masked_interrupt_status
const timer_interrupt_status_t masked_interrupt_status
Timer masked interrupt status.
Definition
spinn_extra.h:294
router_timing_counter_ctrl_t::reset_cycle_count
uint reset_cycle_count
reset cycle counter
Definition
spinn_extra.h:875
sc_clock_mux_t::bdiv
uint bdiv
divide CPU clock B by Bdiv+1 (= 1-4)
Definition
spinn_extra.h:1625
spinnaker_packet_control_byte_t::common::type
uchar type
Should be one of spinnaker_packet_type_t.
Definition
spinn_extra.h:551
sc_mutex_bit_t::bit
uint bit
The only relevant bit in the word.
Definition
spinn_extra.h:1689
comms_tx_control_t::full
uint full
Tx buffer full (sticky)
Definition
spinn_extra.h:619
sdram_ram_config_t::burst
uint burst
burst length (1, 2, 4, 8, 16)
Definition
spinn_extra.h:1199
sdram_direct_command_t::bank
uint bank
bank passed to memory device
Definition
spinn_extra.h:1162
vic_mask_t::interrupt_bits::comm_rx
uint comm_rx
Debug communications receiver interrupt.
Definition
spinn_extra.h:113
ethernet_tx_buffer
static volatile uchar *const ethernet_tx_buffer
Ethernet transmit buffer.
Definition
spinn_extra.h:1971
system_controller_t::io_clear
sc_io_t io_clear
Writing a 1 clears IO register bit.
Definition
spinn_extra.h:1755
vic_control_t::default_vector_address
vic_interrupt_handler_t default_vector_address
default vector address register
Definition
spinn_extra.h:202
router_control
static volatile router_t *const router_control
Router controller registers.
Definition
spinn_extra.h:1073
sdram_controller_t::direct
sdram_direct_command_t direct
direct command
Definition
spinn_extra.h:1264
comms_ctl_t::tx_control
comms_tx_control_t tx_control
Controls packet transmission.
Definition
spinn_extra.h:667
dma_status_t::transfer_done
uint transfer_done
a DMA transfer has completed without error
Definition
spinn_extra.h:400
comms_source_addr_t::p2p_source_id
uint p2p_source_id
16-bit chip source ID for P2P packets
Definition
spinn_extra.h:655
sc_io_t::io_bits::sdram
uint sdram
On-package SDRAM control.
Definition
spinn_extra.h:1574
sdram_dll_user_config1_t::tuning::tune_1
uint tune_1
Fine tuning control on delay line 1.
Definition
spinn_extra.h:1392
router_packet_header_t::flags::parity_error
uint parity_error
packet parity error (error only)
Definition
spinn_extra.h:795
sdram_command
sdram_command
Memory controller commands, for sdram_command_t::command.
Definition
spinn_extra.h:1138
SDRAM_CTL_WAKE
@ SDRAM_CTL_WAKE
Wake.
Definition
spinn_extra.h:1144
SDRAM_CTL_CONFIG
@ SDRAM_CTL_CONFIG
Configure.
Definition
spinn_extra.h:1148
SDRAM_CTL_SLEEP
@ SDRAM_CTL_SLEEP
Sleep.
Definition
spinn_extra.h:1142
SDRAM_CTL_GO
@ SDRAM_CTL_GO
Go.
Definition
spinn_extra.h:1140
SDRAM_CTL_ACTIVE_PAUSE
@ SDRAM_CTL_ACTIVE_PAUSE
Active Pause.
Definition
spinn_extra.h:1150
SDRAM_CTL_PAUSE
@ SDRAM_CTL_PAUSE
Pause.
Definition
spinn_extra.h:1146
vic_mask_t::interrupt_bits::cpu
uint cpu
System Controller interrupt bit set for this processor.
Definition
spinn_extra.h:145
dma_global_control_t::soft_reset_interrupt
uint soft_reset_interrupt
interrupt if dma_status_t::soft_reset set
Definition
spinn_extra.h:446
sdram_dll_status_t::incing
uint incing
Phase comparator is increasing delay.
Definition
spinn_extra.h:1332
vic_mask_t::interrupt_bits::cc_tx_full
uint cc_tx_full
Comms controller transmit buffer full.
Definition
spinn_extra.h:127
sc_clock_mux_t::rtr
uint rtr
clock selector for Router; see sc_clock_source
Definition
spinn_extra.h:1635
sdram_qos_control
static volatile sdram_qos_t *const sdram_qos_control
SDRAM QoS control registers.
Definition
spinn_extra.h:1434
watchdog_control
static volatile watchdog_controller_t *const watchdog_control
Watchdog timer controller registers.
Definition
spinn_extra.h:2058
router_timing_counter_ctrl_t::reset_histogram
uint reset_histogram
reset histogram
Definition
spinn_extra.h:879
watchdog_lock_codes
watchdog_lock_codes
Watchdog timer lock codes, for watchdog_lock_t::whole_value.
Definition
spinn_extra.h:2026
WATCHDOG_LOCK_MAGIC
@ WATCHDOG_LOCK_MAGIC
Unlock the watchdog timer for configuration.
Definition
spinn_extra.h:2030
WATCHDOG_LOCK_RESET
@ WATCHDOG_LOCK_RESET
Put the watchdog timer into normal mode.
Definition
spinn_extra.h:2028
vic_control_t::fiq_status
const vic_mask_t fiq_status
FIQ status register.
Definition
spinn_extra.h:182
vic_mask_t::interrupt_bits::cc_rx_framing_error
uint cc_rx_framing_error
Comms controller received packet framing error.
Definition
spinn_extra.h:125
router_status_t::busy
uint busy
busy - active packet(s) in Router pipeline
Definition
spinn_extra.h:749
dma_description_t::direction
uint direction
read from or write to system bus, see dma_direction_t
Definition
spinn_extra.h:338
dma_t::crcc
const uint crcc
CRC value calculated by CRC block.
Definition
spinn_extra.h:494
sc_misc_control_t::jtag_on_chip
uint jtag_on_chip
select on-chip (1) or off-chip (0) control of JTAG pins
Definition
spinn_extra.h:1544
dma_status_t::queued
uint queued
DMA transfer is queued - registers are full.
Definition
spinn_extra.h:392
router_fixed_route_routing_t::nn_broadcast_links
uint nn_broadcast_links
Nearest-neighbour broadcast link vector.
Definition
spinn_extra.h:921
dma_control_t::clear_timeout_int
uint clear_timeout_int
clear Timeout interrupt request
Definition
spinn_extra.h:378
system_controller_t::pll2_freq_control
sc_pll_control_t pll2_freq_control
PLL2 frequency control.
Definition
spinn_extra.h:1759
router_packet_header_t::flags::time_phase_error
uint time_phase_error
packet time stamp error (error only)
Definition
spinn_extra.h:791
dma_description_t::width
uint width
transfer width, see dma_transfer_unit_t
Definition
spinn_extra.h:344
system_controller_t::cpu_sleep
const sc_sleep_status_t cpu_sleep
CPU sleep (awaiting interrupt) status.
Definition
spinn_extra.h:1767
sdram_command_t::command
uint command
one of sdram_command
Definition
spinn_extra.h:1133
sc_clock_mux_t::pa
uint pa
clock selector for A CPUs (1 2 4 7 8 11 13 14 16); see sc_clock_source
Definition
spinn_extra.h:1617
vic_control_t::soft_int_enable
vic_mask_t soft_int_enable
soft interrupt set register
Definition
spinn_extra.h:192
sdram_dll_status_t::c3
uint c3
Clock faster than strobe 3.
Definition
spinn_extra.h:1328
dma_stats_control_t::clear
uint clear
Clear the statistics registers (if 1)
Definition
spinn_extra.h:472
ethernet_general_status_t::unread_counter
uint unread_counter
Received unread frame count.
Definition
spinn_extra.h:1850
dma_status_t::write_buffer_active
uint write_buffer_active
write buffer is not empty
Definition
spinn_extra.h:396
router_multicast_route_t::routes::links
uint links
The links to route along.
Definition
spinn_extra.h:1005
router_t::diversion
router_diversion_t diversion
divert default packets
Definition
spinn_extra.h:967
ethernet_general_command_t::receive_error_filter
uint receive_error_filter
Receive error filter enable.
Definition
spinn_extra.h:1826
sdram_controller_t::mem_config
sdram_ram_config_t mem_config
memory configuration
Definition
spinn_extra.h:1266
router_error_status_t::overflow
uint overflow
more than one error packet detected
Definition
spinn_extra.h:827
comms_rx_status_t::control_byte
uint control_byte
Control byte of last Rx packet.
Definition
spinn_extra.h:637
vic_control_t::int_enable
vic_mask_t int_enable
interrupt enable set register
Definition
spinn_extra.h:188
router_dump_status_t::overflow
uint overflow
more than one packet dumped
Definition
spinn_extra.h:851
ethernet_interrupt_clear_t::transmit
uint transmit
Clear transmit interrupt request.
Definition
spinn_extra.h:1892
ethernet_controller_t::receive_desc_write
const ethernet_receive_descriptor_pointer_t receive_desc_write
Receive descriptor write pointer.
Definition
spinn_extra.h:1946
ethernet_phy_control_t::irq_invert_disable
uint irq_invert_disable
PHY IRQn invert disable.
Definition
spinn_extra.h:1884
vic_interrupt_vector
static volatile vic_interrupt_handler_t *const vic_interrupt_vector
VIC interrupt handlers. Array of 32 elements.
Definition
spinn_extra.h:224
sdram_dll_user_config1_t::tuning::tune_5
uint tune_5
Fine tuning control on delay line 5.
Definition
spinn_extra.h:1400
spinnaker_packet_control_byte_t::common::timestamp
uchar timestamp
Timestamp (not used for NN packets)
Definition
spinn_extra.h:547
sc_magic_subsystem_map_t::rx_links
uint rx_links
Rx link 0-5.
Definition
spinn_extra.h:1486
watchdog_controller_t::masked_status
const watchdog_status_t masked_status
Masked interrupt status register.
Definition
spinn_extra.h:2046
sdram_dll_status_t::decing
uint decing
Phase comparator is reducing delay.
Definition
spinn_extra.h:1330
ethernet_controller_t::receive_command
uint receive_command
Receive command; any value completes receive.
Definition
spinn_extra.h:1932
ethernet_desc_buffer
static volatile ethernet_receive_descriptor_t *const ethernet_desc_buffer
Ethernet receive descriptor buffer.
Definition
spinn_extra.h:1975
vic_mask_t::interrupt_bits::cc_rx_parity_error
uint cc_rx_parity_error
Comms controller received packet parity error.
Definition
spinn_extra.h:123
sdram_chip_t::match
uint match
address match
Definition
spinn_extra.h:1292
comms_tx_control_t::overrun
uint overrun
Tx buffer overrun (sticky)
Definition
spinn_extra.h:617
sdram_controller_t::refresh
sdram_refresh_t refresh
refresh period
Definition
spinn_extra.h:1268
sdram_dll_user_config0_t::s1
uint s1
Input select for delay line 1 {def, alt, 0, 1}.
Definition
spinn_extra.h:1352
router_p2p_route
router_p2p_route
The possible values of a P2P route.
Definition
spinn_extra.h:1014
ROUTER_P2P_ROUTE_NE
@ ROUTER_P2P_ROUTE_NE
Route north-east.
Definition
spinn_extra.h:1018
ROUTER_P2P_ROUTE_W
@ ROUTER_P2P_ROUTE_W
Route west.
Definition
spinn_extra.h:1022
ROUTER_P2P_ROUTE_N
@ ROUTER_P2P_ROUTE_N
Route north.
Definition
spinn_extra.h:1020
ROUTER_P2P_ROUTE_MONITOR
@ ROUTER_P2P_ROUTE_MONITOR
Definition
spinn_extra.h:1031
ROUTER_P2P_ROUTE_S
@ ROUTER_P2P_ROUTE_S
Route south.
Definition
spinn_extra.h:1026
ROUTER_P2P_ROUTE_E
@ ROUTER_P2P_ROUTE_E
Route east.
Definition
spinn_extra.h:1016
ROUTER_P2P_ROUTE_SW
@ ROUTER_P2P_ROUTE_SW
Route south-west.
Definition
spinn_extra.h:1024
ROUTER_P2P_ROUTE_DROP
@ ROUTER_P2P_ROUTE_DROP
Drop packet.
Definition
spinn_extra.h:1028
system_controller_t::cpu_hard_reset_level
sc_magic_proc_map_t cpu_hard_reset_level
Level control of CPU node resets.
Definition
spinn_extra.h:1731
sc_magic_subsystem_map_t::entire_chip
uint entire_chip
Entire chip (pulse reset only)
Definition
spinn_extra.h:1490
system_controller_t::cpu_soft_reset_pulse
sc_magic_proc_map_t cpu_soft_reset_pulse
Pulse control of CPU resets.
Definition
spinn_extra.h:1735
sdram_dll_t::config1
sdram_dll_user_config1_t config1
Test: fine tune.
Definition
spinn_extra.h:1415
dma_global_control_t::tcm_error_interrupt
uint tcm_error_interrupt
interrupt if dma_status_t::tcm_error set
Definition
spinn_extra.h:440
router_diagnostic_filter_t::pattern_payload
uint pattern_payload
packets with [x1]/without [1x] payload
Definition
spinn_extra.h:985
comms_rx_status_t::error_free
uint error_free
Rx packet received without error.
Definition
spinn_extra.h:643
router_t::diagnostic_counter_control
router_diagnostic_counter_ctrl_t diagnostic_counter_control
diagnostic counter enables
Definition
spinn_extra.h:955
timer_control_t::size
uint size
0 = 16 bit, 1 = 32 bit
Definition
spinn_extra.h:248
sdram_dll_user_config0_t::s5
uint s5
Input select for delay line 5 {def, alt, 0, 1}.
Definition
spinn_extra.h:1360
sc_clock_mux_t::adiv
uint adiv
divide CPU clock A by Adiv+1 (= 1-4)
Definition
spinn_extra.h:1619
vic_mask_t::interrupt_bits::comm_tx
uint comm_tx
Debug communications transmitter interrupt.
Definition
spinn_extra.h:115
comms_rx_status_t::parity_error
uint parity_error
Rx packet parity error (sticky)
Definition
spinn_extra.h:647
sdram_controller_t::cas_latency
sdram_cas_latency_t cas_latency
CAS latency.
Definition
spinn_extra.h:1270
vic_mask_t::interrupt_bits::ethernet_rx
uint ethernet_rx
Ethernet receive frame interrupt.
Definition
spinn_extra.h:149
dma_t::global_control
dma_global_control_t global_control
Control of the DMA device.
Definition
spinn_extra.h:492
sc_pll_control_t::output_divider
uint output_divider
output clock divider
Definition
spinn_extra.h:1587
sc_magic_subsystem_map_t::tx_links
uint tx_links
Tx link 0-5.
Definition
spinn_extra.h:1484
sdram_direct_command_t::address
uint address
address passed to memory device
Definition
spinn_extra.h:1158
sc_frequency_range
sc_frequency_range
Frequency range constants for sc_pll_control_t::freq_range.
Definition
spinn_extra.h:1603
FREQ_50_100
@ FREQ_50_100
50-100 MHz
Definition
spinn_extra.h:1607
FREQ_100_200
@ FREQ_100_200
100-200 MHz
Definition
spinn_extra.h:1609
FREQ_25_50
@ FREQ_25_50
25-50 MHz
Definition
spinn_extra.h:1605
FREQ_200_400
@ FREQ_200_400
200-400 MHz
Definition
spinn_extra.h:1611
sdram_dll_control
static volatile sdram_dll_t *const sdram_dll_control
SDRAM delay-locked-loop control registers.
Definition
spinn_extra.h:1440
dma_t::status
const dma_status_t status
Status of DMA and other transfers.
Definition
spinn_extra.h:490
system_controller_t::monitor_id
sc_monitor_id_t monitor_id
ID of Monitor Processor.
Definition
spinn_extra.h:1743
router_t::status
const router_status_t status
Router status.
Definition
spinn_extra.h:929
comms_control
static volatile comms_ctl_t *const comms_control
Communications controller registers.
Definition
spinn_extra.h:690
comms_tx_control_t::control_byte
uint control_byte
control byte of next sent packet
Definition
spinn_extra.h:611
vic_control
static volatile vic_control_t *const vic_control
VIC registers.
Definition
spinn_extra.h:220
sdram_ram_config_t::active
uint active
active chips: number for refresh generation
Definition
spinn_extra.h:1203
comms_tx_control_t::empty
uint empty
Tx buffer empty.
Definition
spinn_extra.h:621
sdram_timing_config_t::t_ras
uint t_ras
RAS to precharge delay.
Definition
spinn_extra.h:1234
ethernet_phy_control_t::smi_out_enable
uint smi_out_enable
SMI data output enable.
Definition
spinn_extra.h:1880
router_p2p_route_table
static volatile router_p2p_table_entry_t *const router_p2p_route_table
Router peer-to-peer route table.
Definition
spinn_extra.h:1088
vic_control_t::int_select
vic_mask_t int_select
interrupt select register
Definition
spinn_extra.h:186
sdram_ram_config_t::power_down_delay
uint power_down_delay
number of memory cycles before auto-power-down
Definition
spinn_extra.h:1193
ethernet_receive_descriptor_t::length
uint length
Received packet length.
Definition
spinn_extra.h:1956
sc_link_disable_t::tx_disable
uint tx_disable
disables the corresponding link transmitter
Definition
spinn_extra.h:1699
router_status_t::interrupt_active_error
uint interrupt_active_error
error packet interrupt active
Definition
spinn_extra.h:759
dma_t::sdram_address
void * sdram_address
DMA address on the system interface.
Definition
spinn_extra.h:482
dma_transfer_unit_t
dma_transfer_unit_t
DMA burst width, see dma_description_t::width.
Definition
spinn_extra.h:360
DMA_TRANSFER_DOUBLE_WORD
@ DMA_TRANSFER_DOUBLE_WORD
Transfer in double-words.
Definition
spinn_extra.h:364
DMA_TRANSFER_WORD
@ DMA_TRANSFER_WORD
Transfer in words.
Definition
spinn_extra.h:362
sc_magic
sc_magic
System controller magic numbers.
Definition
spinn_extra.h:1783
SYSTEM_CONTROLLER_MAGIC_NUMBER
@ SYSTEM_CONTROLLER_MAGIC_NUMBER
Magic number for enabling writing to critical fields.
Definition
spinn_extra.h:1785
sdram_qos_t::maximum
uint maximum
maximum QoS
Definition
spinn_extra.h:1282
ethernet_tx_length_t::tx_length
uint tx_length
Length of transmit frame (60 - 1514 bytes)
Definition
spinn_extra.h:1860
sdram_dll_user_config0_t::s3
uint s3
Input select for delay line 3 {def, alt, 0, 1}.
Definition
spinn_extra.h:1356
sdram_timing_config_t::t_wr
uint t_wr
write to precharge delay
Definition
spinn_extra.h:1246
system_controller_t::set_cpu_ok
uint set_cpu_ok
Writing a 1 sets a CPU OK bit.
Definition
spinn_extra.h:1725
timer_controller_t::control
timer_control_t control
Timer control register.
Definition
spinn_extra.h:288
system_controller_t::processor_disable
sc_magic_proc_map_t processor_disable
Each bit disables a processor.
Definition
spinn_extra.h:1719
router_packet_header_t::flags::control
uint control
control byte; really a spinnaker_packet_control_byte_t
Definition
spinn_extra.h:787
spinnaker_packet_control_byte_t::fr::emergency_routing
uchar emergency_routing
Emergency routing control.
Definition
spinn_extra.h:587
router_timing_counter_ctrl_t::enable_emergency_active_count
uint enable_emergency_active_count
enable emergency router active cycle counter
Definition
spinn_extra.h:869
router_diagnostic_filter_t::pattern_local
uint pattern_local
local [x1]/non-local[1x] packet source
Definition
spinn_extra.h:987
router_t::error::status
const router_error_status_t status
error packet status
Definition
spinn_extra.h:939
timer_control_t::interrupt_enable
uint interrupt_enable
enable interrupt (1 = enabled)
Definition
spinn_extra.h:254
timer_controller_t::raw_interrupt_status
const timer_interrupt_status_t raw_interrupt_status
Timer raw interrupt status.
Definition
spinn_extra.h:292
ethernet_receive_pointer_t::ptr
uint ptr
Receive frame buffer read pointer.
Definition
spinn_extra.h:1904
vic_mask_t::interrupt_bits::dma_timeout
uint dma_timeout
DMA controller transfer timed out.
Definition
spinn_extra.h:137
sdram_controller_t::command
sdram_command_t command
PL340 command.
Definition
spinn_extra.h:1262
sdram_timing_config_t::t_rc
uint t_rc
active bank x to active bank x delay
Definition
spinn_extra.h:1236
dma_t::description
dma_description_t description
DMA transfer descriptor; note that setting this commits a DMA.
Definition
spinn_extra.h:486
dma_t::tcm_address
void * tcm_address
DMA address on the TCM interface.
Definition
spinn_extra.h:484
sc_clock_mux_t::sdiv
uint sdiv
divide System AHB clock by Sdiv+1 (= 1-4)
Definition
spinn_extra.h:1643
system_controller_t::subsystem_reset_pulse
sc_magic_subsystem_map_t subsystem_reset_pulse
Pulse control of subsystem resets.
Definition
spinn_extra.h:1739
router_fixed_route_routing_t::fr_processors
uint fr_processors
The physical processors to route FR packets to.
Definition
spinn_extra.h:917
router_timing_counter_ctrl_t::reset_emergency_active_count
uint reset_emergency_active_count
reset emergency router active cycle counter
Definition
spinn_extra.h:877
router_t::timing_counter_control
router_timing_counter_ctrl_t timing_counter_control
timing counter controls
Definition
spinn_extra.h:957
sdram_timing_config_t::t_rfc
uint t_rfc
auto-refresh command time
Definition
spinn_extra.h:1240
watchdog_lock_t::whole_value
uint whole_value
Whole value of lock; see watchdog_lock_codes.
Definition
spinn_extra.h:2022
ethernet_general_command_t::receive_multicast
uint receive_multicast
Receive multicast packets enable.
Definition
spinn_extra.h:1830
router_control_t::error_interrupt_enable
uint error_interrupt_enable
enable error packet interrupt
Definition
spinn_extra.h:721
router_t::dump::outputs
const router_dump_outputs_t outputs
dumped packet intended destinations
Definition
spinn_extra.h:950
spinnaker_packet_control_byte_t::mc::emergency_routing
uchar emergency_routing
Emergency routing control.
Definition
spinn_extra.h:558
dma_global_control_t::bridge_buffer_enable
uint bridge_buffer_enable
enable Bridge write buffer
Definition
spinn_extra.h:428
router_t::dump::key
const uint key
dumped packet routing word
Definition
spinn_extra.h:946
ethernet_controller_t::receive_read
const ethernet_receive_pointer_t receive_read
Receive frame buffer read pointer.
Definition
spinn_extra.h:1940
vic_mask_t::interrupt_bits::timer1
uint timer1
Counter/timer interrupt 1.
Definition
spinn_extra.h:117
sdram_dll_user_config0_t::L
uint L
Force 3-phase bar-code control inputs.
Definition
spinn_extra.h:1376
sdram_dll_user_config0_t::test_5
uint test_5
Substitute delay line 5 for 4 for testing.
Definition
spinn_extra.h:1370
system_controller_t::gpio_pull_up_down_enable
sc_io_t gpio_pull_up_down_enable
General-purpose IO pull up/down enable.
Definition
spinn_extra.h:1747
vic_mask_t::value
uint value
Whole mask as integer.
Definition
spinn_extra.h:174
dma_status_t::write_buffer_error
uint write_buffer_error
a buffered write transfer has failed
Definition
spinn_extra.h:418
sc_link_disable_t::security_code
uint security_code
SYSTEM_CONTROLLER_MAGIC_NUMBER to enable write
Definition
spinn_extra.h:1707
sc_temperature_t::start
uint start
start temperature measurement
Definition
spinn_extra.h:1681
vic_control_t::irq_status
const vic_mask_t irq_status
IRQ status register.
Definition
spinn_extra.h:180
router_control_t::drop_wait_time
uint drop_wait_time
wait2; wait time before dropping packet after entering emergency routing
Definition
spinn_extra.h:741
router_control_t::route_packets_enable
uint route_packets_enable
enable packet routing
Definition
spinn_extra.h:719
dma_t::current_sdram_address
const void * current_sdram_address
Active system address.
Definition
spinn_extra.h:508
router_diversion_t::L3
uint L3
Diversion rule for link 3.
Definition
spinn_extra.h:893
spinnaker_packet_type_t
spinnaker_packet_type_t
SpiNNaker packet type codes.
Definition
spinn_extra.h:595
SPINNAKER_PACKET_TYPE_NN
@ SPINNAKER_PACKET_TYPE_NN
Nearest-neighbour packet.
Definition
spinn_extra.h:601
SPINNAKER_PACKET_TYPE_FR
@ SPINNAKER_PACKET_TYPE_FR
Fixed-route packet.
Definition
spinn_extra.h:603
SPINNAKER_PACKET_TYPE_P2P
@ SPINNAKER_PACKET_TYPE_P2P
Peer-to-peer packet.
Definition
spinn_extra.h:599
SPINNAKER_PACKET_TYPE_MC
@ SPINNAKER_PACKET_TYPE_MC
Multicast packet.
Definition
spinn_extra.h:597
sc_clock_mux_t::invert_b
uint invert_b
invert CPU clock B
Definition
spinn_extra.h:1647
sdram_ram_config_t::auto_power_down
uint auto_power_down
auto-power-down memory when inactive
Definition
spinn_extra.h:1195
sdram_direct_command_t::cmd
uint cmd
command passed to memory device
Definition
spinn_extra.h:1164
dma_status_t::crc_error
uint crc_error
the calculated and received CRCs differ
Definition
spinn_extra.h:406
comms_rx_status_t::framing_error
uint framing_error
Rx packet framing error (sticky)
Definition
spinn_extra.h:645
router_p2p_table_entry_t::routes::route2
router_p2p_route route2
Second packed route.
Definition
spinn_extra.h:1041
router_packet_header_t::flags::framing_error
uint framing_error
packet framing error (error only)
Definition
spinn_extra.h:793
router_control_t::count_parity_errors
uint count_parity_errors
enable count of packet parity errors
Definition
spinn_extra.h:729
watchdog_status_t::interrupted
uint interrupted
True if interrupt asserted.
Definition
spinn_extra.h:2007
ethernet_controller_t::receive_desc_read
const ethernet_receive_descriptor_pointer_t receive_desc_read
Receive descriptor read pointer.
Definition
spinn_extra.h:1944
ethernet_general_command_t::hardware_byte_reorder_disable
uint hardware_byte_reorder_disable
Disable hardware byte reordering.
Definition
spinn_extra.h:1840
sdram_ram_config_t::stop_clock
uint stop_clock
stop memory clock when no access
Definition
spinn_extra.h:1197
sc_pll_control_t::input_multiplier
uint input_multiplier
input clock multiplier
Definition
spinn_extra.h:1583
dma_global_control_t::transfer2_done_interrupt
uint transfer2_done_interrupt
interrupt if dma_status_t::transfer2_done set
Definition
spinn_extra.h:434
dma_control_t::uncommit
uint uncommit
setting this bit uncommits a queued transfer
Definition
spinn_extra.h:370
sc_temperature_t::temperature
uint temperature
temperature sensor reading
Definition
spinn_extra.h:1675
ASSERT_WORD_SIZED
#define ASSERT_WORD_SIZED(type_ident)
Generates valid code if the named type is one word long, and invalid code otherwise.
Definition
spinn_extra.h:60
spinnaker_packet_control_byte_t::common::payload
uchar payload
Payload-word-present flag.
Definition
spinn_extra.h:545
sc_clock_source
sc_clock_source
System controller clock sources.
Definition
spinn_extra.h:1653
CLOCK_SRC_PLL2
@ CLOCK_SRC_PLL2
PLL2.
Definition
spinn_extra.h:1659
CLOCK_SRC_EXT
@ CLOCK_SRC_EXT
external 10MHz clock input
Definition
spinn_extra.h:1655
CLOCK_SRC_EXT4
@ CLOCK_SRC_EXT4
external 10MHz clock divided by 4
Definition
spinn_extra.h:1661
CLOCK_SRC_PLL1
@ CLOCK_SRC_PLL1
PLL1.
Definition
spinn_extra.h:1657
sdram_ram_config_t::row
uint row
number of row address bits (11-16)
Definition
spinn_extra.h:1189
sc_magic_proc_map_t::select
uint select
Bit-map for selecting a processor.
Definition
spinn_extra.h:1466
dma_status_t::transferring
uint transferring
DMA transfer in progress.
Definition
spinn_extra.h:388
sdram_qos_t::minimum
uint minimum
minimum QoS
Definition
spinn_extra.h:1280
system_controller_t::clear_cpu_irq
sc_magic_proc_map_t clear_cpu_irq
Writing a 1 clears a processor’s interrupt line.
Definition
spinn_extra.h:1723
sc_misc_control_t::clk32
uint clk32
read value on Clk32 pin
Definition
spinn_extra.h:1550
ethernet_phy_control_t::smi_output
uint smi_output
SMI data output.
Definition
spinn_extra.h:1878
sdram_timing_config_t::t_rrd
uint t_rrd
active bank x to active bank y delay
Definition
spinn_extra.h:1244
system_controller_t::pll1_freq_control
sc_pll_control_t pll1_freq_control
PLL1 frequency control.
Definition
spinn_extra.h:1757
spinnaker_packet_control_byte_t::common::parity
uchar parity
Packet parity.
Definition
spinn_extra.h:543
vic_mask_t::interrupt_bits::int1
uint int1
External interrupt request 1.
Definition
spinn_extra.h:167
router_packet_header_t::flags::route
uint route
Rx route field of packet.
Definition
spinn_extra.h:789
sdram_control
static volatile sdram_controller_t *const sdram_control
SDRAM interface control registers.
Definition
spinn_extra.h:1431
comms_rx_status_t::multicast
uint multicast
error-free multicast packet received
Definition
spinn_extra.h:627
ethernet_controller_t::phy_control
ethernet_phy_control_t phy_control
PHY control.
Definition
spinn_extra.h:1936
vic_vector_control_t::enable
uint enable
interrupt enable
Definition
spinn_extra.h:210
router_p2p_table_entry_t::routes::route5
router_p2p_route route5
Fifth packed route.
Definition
spinn_extra.h:1047
timer_controller_t::background_load_value
uint background_load_value
Background load value for Timer.
Definition
spinn_extra.h:296
sdram_dll_t::config0
sdram_dll_user_config0_t config0
Test: control.
Definition
spinn_extra.h:1413
router_key_table
static volatile uint *const router_key_table
Router multicast key table (write only!)
Definition
spinn_extra.h:1084
router_p2p_table_entry_t::routes::route1
router_p2p_route route1
First packed route.
Definition
spinn_extra.h:1039
dma_t::crcr
const uint crcr
CRC value in received block.
Definition
spinn_extra.h:496
comms_rx_status_t::point_to_point
uint point_to_point
error-free point-to-point packet received
Definition
spinn_extra.h:629
sdram_timing_config_t::t_wtr
uint t_wtr
write to read delay
Definition
spinn_extra.h:1248
dma_status_t::soft_reset
uint soft_reset
a soft reset of the DMA controller has happened
Definition
spinn_extra.h:414
vic_mask_t::interrupt_bits::timer2
uint timer2
Counter/timer interrupt 2.
Definition
spinn_extra.h:119
sdram_register_maxima
sdram_register_maxima
Maximum register IDs.
Definition
spinn_extra.h:1300
SDRAM_QOS_MAX
@ SDRAM_QOS_MAX
Maximum memory QoS register.
Definition
spinn_extra.h:1302
SDRAM_CHIP_MAX
@ SDRAM_CHIP_MAX
Maximum memory chip configuration register.
Definition
spinn_extra.h:1304
dma_t::timeout
dma_timeout_t timeout
Timeout value.
Definition
spinn_extra.h:498
sc_pll_control_t::power_up
uint power_up
Power UP.
Definition
spinn_extra.h:1593
spinnaker_packet_control_byte_t::nn::mem_or_normal
uchar mem_or_normal
Type indicator.
Definition
spinn_extra.h:578
router_t::emergency_active_cycle_count
const uint emergency_active_cycle_count
counts emergency router active cycles
Definition
spinn_extra.h:961
comms_rx_status_t::route
uint route
Rx route field from packet.
Definition
spinn_extra.h:639
ethernet_control
static volatile ethernet_controller_t *const ethernet_control
Ethernet MII controller registers.
Definition
spinn_extra.h:1978
sc_misc_control_t::ethermux
uint ethermux
read value on Ethermux pin
Definition
spinn_extra.h:1548
vic_mask_t::interrupt_bits::int0
uint int0
External interrupt request 0.
Definition
spinn_extra.h:165
dma_global_control_t::user_abort_interrupt
uint user_abort_interrupt
interrupt if dma_status_t::user_abort set
Definition
spinn_extra.h:444
sdram_dll_user_config0_t::test_incing
uint test_incing
Force Incing (if ID = 1)
Definition
spinn_extra.h:1366
sdram_controller_t::status
const sdram_status_t status
memory controller status
Definition
spinn_extra.h:1260
router_diversion_t::L5
uint L5
Diversion rule for link 5.
Definition
spinn_extra.h:897
comms_rx_status_t::fixed_route
uint fixed_route
error-free fixed-route packet received
Definition
spinn_extra.h:633
spinnaker_packet_control_byte_t::p2p::seq_code
uchar seq_code
Sequence code.
Definition
spinn_extra.h:567
router_diagnostic_filter_t::type
uint type
packet type: fr, nn, p2p, mc
Definition
spinn_extra.h:975
sdram_timing_config_t::t_xsr
uint t_xsr
exit self-refresh command time
Definition
spinn_extra.h:1252
dma_status_t::transfer2_done
uint transfer2_done
2nd DMA transfer has completed without error
Definition
spinn_extra.h:402
dma_status_t::timeout
uint timeout
a burst transfer has not completed in time
Definition
spinn_extra.h:404
dma_global_control_t::timer
uint timer
system-wide slow timer status and clear
Definition
spinn_extra.h:454
timer_controller_t::load_value
uint load_value
Load value for Timer.
Definition
spinn_extra.h:284
dma_control_t::abort
uint abort
end current transfer and discard data
Definition
spinn_extra.h:372
router_mask_table
static volatile uint *const router_mask_table
Router multicast mask table (write only!)
Definition
spinn_extra.h:1086
system_controller_t::io_port
sc_io_t io_port
I/O pin output register.
Definition
spinn_extra.h:1749
comms_ctl_t::tx_key
uint tx_key
Send MC key/P2P dest ID & seq code; writing this commits a send.
Definition
spinn_extra.h:671
sdram_dll_status_t::locked
uint locked
Phase comparator is locked.
Definition
spinn_extra.h:1334
router_diversion_t::L0
uint L0
Diversion rule for link 0.
Definition
spinn_extra.h:887
dma_global_control_t::transfer_done_interrupt
uint transfer_done_interrupt
interrupt if dma_status_t::transfer_done set
Definition
spinn_extra.h:432
sc_sleep_status_t::status
uint status
ARM968 STANDBYWFI signal for each core.
Definition
spinn_extra.h:1667
sc_clock_mux_t::sys
uint sys
clock selector for System AHB components; see sc_clock_source
Definition
spinn_extra.h:1641
sdram_status_t::width
uint width
Width of external memory: 2’b01 = 32 bits.
Definition
spinn_extra.h:1117
sdram_direct_command_t::chip
uint chip
chip number
Definition
spinn_extra.h:1166
ethernet_general_command_t::transmit
uint transmit
Transmit system enable.
Definition
spinn_extra.h:1820
router_diagnostic_filter_t::pattern_default
uint pattern_default
default [x1]/non-default [1x] routed packets
Definition
spinn_extra.h:983
sdram_timing_config_t::t_rcd
uint t_rcd
RAS to CAS minimum delay.
Definition
spinn_extra.h:1238
ethernet_receive_descriptor_pointer_t::rollover
uint rollover
Rollover bit - toggles on address wrap-around.
Definition
spinn_extra.h:1916
ethernet_controller_t::mac_address
uint64 mac_address
MAC address; low 48 bits only.
Definition
spinn_extra.h:1934
router_t::dump::header
const router_packet_header_t header
dumped packet control byte and flags
Definition
spinn_extra.h:944
sdram_cas_latency_t::half_cycle
uint half_cycle
CAS half cycle - must be set to 1’b0.
Definition
spinn_extra.h:1219
ethernet_general_status_t::drop_counter
uint drop_counter
Receive dropped frame count.
Definition
spinn_extra.h:1854
vic_mask_t::interrupt_bits::cc_rx_p2p
uint cc_rx_p2p
Comms controller point-to-point packet received.
Definition
spinn_extra.h:159
sdram_dll_user_config0_t::s0
uint s0
Input select for delay line 0 {def, alt, 0, 1}.
Definition
spinn_extra.h:1350
sdram_dll_user_config0_t::enable
uint enable
Enable DLL (0 = reset DLL)
Definition
spinn_extra.h:1380
router_p2p_table_entry_t::routes::route8
router_p2p_route route8
Eighth packed route.
Definition
spinn_extra.h:1053
router_timing_counter_ctrl_t::enable_cycle_count
uint enable_cycle_count
enable cycle counter
Definition
spinn_extra.h:867
router_diagnostic_filter_t::counter_event_interrupt_active
uint counter_event_interrupt_active
counter interrupt active: I = E AND C
Definition
spinn_extra.h:997
sdram_ram_config_t::qos
uint qos
selects the 4-bit QoS field from the AXI ARID
Definition
spinn_extra.h:1201
ethernet_phy_control_t::smi_clock
uint smi_clock
SMI clock (active rising)
Definition
spinn_extra.h:1882
router_fixed_route_routing_t::fr_links
uint fr_links
The links to route FR packets along.
Definition
spinn_extra.h:915
ethernet_general_command_t::receive_broadcast
uint receive_broadcast
Receive broadcast packets enable.
Definition
spinn_extra.h:1832
router_p2p_table_entry_t::routes::route4
router_p2p_route route4
Fourth packed route.
Definition
spinn_extra.h:1045
vic_control_t::vector_address
vic_interrupt_handler_t vector_address
current vector address register
Definition
spinn_extra.h:200
router_dump_outputs_t::link
uint link
Tx link transmit error caused packet dump.
Definition
spinn_extra.h:835
vic_interrupt_control
static volatile vic_vector_control_t *const vic_interrupt_control
VIC individual interrupt control. Array of 32 elements.
Definition
spinn_extra.h:227
router_control_t::time_phase
uint time_phase
time phase (c.f. packet time stamps)
Definition
spinn_extra.h:731
vic_mask_t::interrupt_bits::cc_rx_mc
uint cc_rx_mc
Comms controller multicast packet received.
Definition
spinn_extra.h:157
router_diversion_rule_t
router_diversion_rule_t
Diversion rules for the fields of router_diversion_t.
Definition
spinn_extra.h:903
ROUTER_DIVERSION_NORMAL
@ ROUTER_DIVERSION_NORMAL
Send on default route.
Definition
spinn_extra.h:905
ROUTER_DIVERSION_DESTROY
@ ROUTER_DIVERSION_DESTROY
Destroy default-routed packets.
Definition
spinn_extra.h:909
ROUTER_DIVERSION_MONITOR
@ ROUTER_DIVERSION_MONITOR
Divert to local monitor.
Definition
spinn_extra.h:907
vic_mask_t::interrupt_bits::router_dump
uint router_dump
Router packet dumped - indicates failed delivery.
Definition
spinn_extra.h:141
router_control_t::count_framing_errors
uint count_framing_errors
enable count of packet framing errors
Definition
spinn_extra.h:727
timer_control_t::pre_divide
uint pre_divide
divide input clock (see timer_pre_divide)
Definition
spinn_extra.h:250
router_multicast_route_t::value
uint value
Overall entry packed as number.
Definition
spinn_extra.h:1010
system_controller_t::clock_mux_control
sc_clock_mux_t clock_mux_control
Clock multiplexer controls.
Definition
spinn_extra.h:1765
router_error_status_t::framing_error
uint framing_error
packet framing error (sticky)
Definition
spinn_extra.h:823
router_control_t::count_timestamp_errors
uint count_timestamp_errors
enable count of packet time stamp errors
Definition
spinn_extra.h:725
ethernet_controller_t::command
ethernet_general_command_t command
General command.
Definition
spinn_extra.h:1924
dma_t::control
dma_control_t control
Control DMA transfer.
Definition
spinn_extra.h:488
sdram_controller_t::timing_config
sdram_timing_config_t timing_config
timing configuration
Definition
spinn_extra.h:1272
sdram_refresh_t::period
uint period
memory refresh period in memory clock cycles
Definition
spinn_extra.h:1211
sc_reset_codes
sc_reset_codes
System controller chip reset reasons.
Definition
spinn_extra.h:1506
SC_RESET_CODE_POR
@ SC_RESET_CODE_POR
Power-on reset.
Definition
spinn_extra.h:1508
SC_RESET_CODE_REC
@ SC_RESET_CODE_REC
Reset entire chip (sc_magic_subsystem_map_t::entire_chip)
Definition
spinn_extra.h:1514
SC_RESET_CODE_WDI
@ SC_RESET_CODE_WDI
Watchdog interrupt.
Definition
spinn_extra.h:1516
SC_RESET_CODE_WDR
@ SC_RESET_CODE_WDR
Watchdog reset.
Definition
spinn_extra.h:1510
SC_RESET_CODE_UR
@ SC_RESET_CODE_UR
User reset.
Definition
spinn_extra.h:1512
timer_control_t::periodic_mode
uint periodic_mode
0 = free-running; 1 = periodic
Definition
spinn_extra.h:256
sc_link_disable_t::parity_control
uint parity_control
Router parity control.
Definition
spinn_extra.h:1703
router_t::unblocked_count
const uint unblocked_count
counts packets that do not wait to be issued
Definition
spinn_extra.h:963
comms_ctl_t::source_addr
comms_source_addr_t source_addr
P2P source address.
Definition
spinn_extra.h:680
vic_control_t::protection
bool protection
protection register
Definition
spinn_extra.h:196
vic_mask_t::interrupt_bits::dma_error
uint dma_error
DMA controller error.
Definition
spinn_extra.h:135
sc_temperature_t::sample_finished
uint sample_finished
temperature measurement finished
Definition
spinn_extra.h:1677
dma_global_control_t::timeout_interrupt
uint timeout_interrupt
interrupt if dma_status_t::timeout set
Definition
spinn_extra.h:436
sc_io_t::io_bits::ethernet_transmit
uint ethernet_transmit
Ethernet MII TxD port.
Definition
spinn_extra.h:1568
sdram_status_t::banks
uint banks
Fixed at 1’b01 = 4 banks on a chip.
Definition
spinn_extra.h:1123
dma_status_t::tcm_error
uint tcm_error
the TCM AHB interface has signalled an error
Definition
spinn_extra.h:408
vic_mask_t::interrupt_bits::cc_rx_nn
uint cc_rx_nn
Comms controller nearest neighbour packet received.
Definition
spinn_extra.h:161
router_output_stage
router_output_stage
Stages in router_status_t::output_stage.
Definition
spinn_extra.h:765
ROUTER_OUTPUT_STAGE_WAIT1
@ ROUTER_OUTPUT_STAGE_WAIT1
output stage is blocked in wait1
Definition
spinn_extra.h:771
ROUTER_OUTPUT_STAGE_EMPTY
@ ROUTER_OUTPUT_STAGE_EMPTY
output stage is empty
Definition
spinn_extra.h:767
ROUTER_OUTPUT_STAGE_FULL
@ ROUTER_OUTPUT_STAGE_FULL
output stage is full but unblocked
Definition
spinn_extra.h:769
ROUTER_OUTPUT_STAGE_WAIT2
@ ROUTER_OUTPUT_STAGE_WAIT2
output stage is blocked in wait2
Definition
spinn_extra.h:773
timer_control_t::one_shot
uint one_shot
0 = wrapping mode, 1 = one shot
Definition
spinn_extra.h:246
sdram_timing_config_t::t_esr
uint t_esr
self-refresh command time
Definition
spinn_extra.h:1254
system_controller_t::cpu_hard_reset_pulse
sc_magic_proc_map_t cpu_hard_reset_pulse
Pulse control of CPU node resets.
Definition
spinn_extra.h:1737
vic_control_t::soft_int_disable
vic_mask_t soft_int_disable
soft interrupt clear register
Definition
spinn_extra.h:194
sc_magic_subsystem_map_t::comms_noc
uint comms_noc
Communications NoC.
Definition
spinn_extra.h:1482
vic_control_t::int_disable
vic_mask_t int_disable
interrupt enable clear register
Definition
spinn_extra.h:190
dma_global_control_t::axi_error_interrupt
uint axi_error_interrupt
interrupt if dma_status_t::axi_error set
Definition
spinn_extra.h:442
vic_control_t::raw_status
const vic_mask_t raw_status
raw interrupt status register
Definition
spinn_extra.h:184
sc_monitor_id_t::reset_on_watchdog
uint reset_on_watchdog
Reset Monitor Processor on Watchdog interrupt.
Definition
spinn_extra.h:1530
router_error_status_t::error
uint error
error packet detected
Definition
spinn_extra.h:829
router_t::error::header
const router_packet_header_t header
error packet control byte and flags
Definition
spinn_extra.h:933
dma_control_t::clear_done_int
uint clear_done_int
clear Done interrupt request
Definition
spinn_extra.h:376
ethernet_general_command_t::receive
uint receive
Receive system enable.
Definition
spinn_extra.h:1822
router_packet_header_t::word
uint word
as a whole word
Definition
spinn_extra.h:811
router_packet_header_t::flags::time_phase
uint time_phase
time phase when packet received/dumped
Definition
spinn_extra.h:783
vic_mask_t::interrupt_bits::slow_clock
uint slow_clock
System-wide slow (nominally 32 KHz) timer interrupt.
Definition
spinn_extra.h:153
system_controller_t::clear_cpu_ok
uint clear_cpu_ok
Writing a 1 clears a CPU OK bit.
Definition
spinn_extra.h:1727
sc_monitor_id_t::monitor_id
uint monitor_id
Monitor processor identifier.
Definition
spinn_extra.h:1522
router_diagnostic_counter
static volatile uint *const router_diagnostic_counter
Router diagnostic counters.
Definition
spinn_extra.h:1078
router_dump_status_t::processor
uint processor
Fascicle Proc link error caused dump (sticky)
Definition
spinn_extra.h:847
router_dump_status_t::link
uint link
Tx link error caused dump (sticky)
Definition
spinn_extra.h:845
dma_t::current_description
const dma_description_t current_description
Active transfer description.
Definition
spinn_extra.h:512
sdram_chip_control
static volatile sdram_chip_t *const sdram_chip_control
SDRAM chip control registers.
Definition
spinn_extra.h:1437
router_p2p_table_entry_t::routes::route6
router_p2p_route route6
Sixth packed route.
Definition
spinn_extra.h:1049
router_t::error::payload
const uint payload
error packet data payload
Definition
spinn_extra.h:937
sdram_ram_config_t::auto_precharge_position
uint auto_precharge_position
position of auto-pre-charge bit (10/8)
Definition
spinn_extra.h:1191
sc_io_t::io_bits::jtag
uint jtag
JTAG interface.
Definition
spinn_extra.h:1570
sdram_dll_status_t::s1
uint s1
Strobe 1 faster than Clock.
Definition
spinn_extra.h:1318
router_t::cycle_count
const uint cycle_count
counts Router clock cycles
Definition
spinn_extra.h:959
sc_magic_subsystem_map_t::sdram
uint sdram
PL340 SDRAM controller.
Definition
spinn_extra.h:1478
dma_status_t::axi_error
uint axi_error
the AXI interface (SDRAM) has signalled a transfer error
Definition
spinn_extra.h:410
sdram_dll_t::status
const sdram_dll_status_t status
Status.
Definition
spinn_extra.h:1411
sdram_chip_t::orientation
uint orientation
bank-row-column/row-bank-column
Definition
spinn_extra.h:1294
ethernet_rx_buffer
static volatile uchar *const ethernet_rx_buffer
Ethernet receive buffer.
Definition
spinn_extra.h:1973
sdram_dll_user_config1_t::tuning::tune_4
uint tune_4
Fine tuning control on delay line 4.
Definition
spinn_extra.h:1398
sdram_dll_status_t::meter
uint meter
Current position of bar-code output.
Definition
spinn_extra.h:1310
ethernet_general_command_t::receive_unicast
uint receive_unicast
Receive unicast packets enable.
Definition
spinn_extra.h:1828
sdram_dll_user_config0_t::R
uint R
Force 3-phase bar-code control inputs.
Definition
spinn_extra.h:1372
sdram_dll_user_config0_t::test_decing
uint test_decing
Force Decing (if ID = 1)
Definition
spinn_extra.h:1364
dma_control_t::restart
uint restart
resume transfer (clears DMA errors)
Definition
spinn_extra.h:374
sdram_status_t::monitors
uint monitors
Number of exclusive access monitors (0, 1, 2, 4)
Definition
spinn_extra.h:1125
system_controller_t::subsystem_reset_level
sc_magic_subsystem_map_t subsystem_reset_level
Level control of subsystem resets.
Definition
spinn_extra.h:1733
dma_status_t::user_abort
uint user_abort
the user has aborted the transfer (via dma_control_t::abort)
Definition
spinn_extra.h:412
watchdog_control_t::interrupt_enable
uint interrupt_enable
Enable Watchdog counter and interrupt (1)
Definition
spinn_extra.h:1997
watchdog_controller_t::interrupt_clear
uint interrupt_clear
Interrupt clear register; any written value will do.
Definition
spinn_extra.h:2042
sc_magic_proc_map_t::security_code
uint security_code
SYSTEM_CONTROLLER_MAGIC_NUMBER to enable write
Definition
spinn_extra.h:1470
router_packet_header_t::control_field_bits::payload
uint payload
payload-present field from control byte
Definition
spinn_extra.h:804
vic_mask_t::interrupt_bits::software
uint software
Local software interrupt generation.
Definition
spinn_extra.h:111
timer1_control
static volatile timer_controller_t *const timer1_control
Timer 1 control registers.
Definition
spinn_extra.h:305
sdram_dll_user_config0_t::M
uint M
Force 3-phase bar-code control inputs.
Definition
spinn_extra.h:1374
sc_link_disable_t::rx_disable
uint rx_disable
disables the corresponding link receiver
Definition
spinn_extra.h:1695
dma_control
static volatile dma_t *const dma_control
DMA control registers.
Definition
spinn_extra.h:527
comms_source_addr_t::route
uint route
Set 'fake' route in packet.
Definition
spinn_extra.h:659
ethernet_controller_t::transmit_length
ethernet_tx_length_t transmit_length
Transmit frame length.
Definition
spinn_extra.h:1928
ethernet_interrupt_clear_t::receive
uint receive
Clear receive interrupt request.
Definition
spinn_extra.h:1896
sdram_direct_command
sdram_direct_command
Memory direct commands, for sdram_direct_command_t::cmd.
Definition
spinn_extra.h:1173
SDRAM_DIRECT_MODEREG
@ SDRAM_DIRECT_MODEREG
Mode Register.
Definition
spinn_extra.h:1179
SDRAM_DIRECT_AUTOREFRESH
@ SDRAM_DIRECT_AUTOREFRESH
Auto-Refresh.
Definition
spinn_extra.h:1177
SDRAM_DIRECT_PRECHARGE
@ SDRAM_DIRECT_PRECHARGE
Precharge.
Definition
spinn_extra.h:1175
SDRAM_DIRECT_NOP
@ SDRAM_DIRECT_NOP
No-op.
Definition
spinn_extra.h:1181
vic_mask_t::interrupt_bits::cc_tx_empty
uint cc_tx_empty
Comms controller transmit buffer empty.
Definition
spinn_extra.h:131
comms_ctl_t::rx_data
const uint rx_data
32-bit received data
Definition
spinn_extra.h:675
sc_misc_control_t::jtag_rtck
uint jtag_rtck
read value on JTAG_RTCK pin
Definition
spinn_extra.h:1554
comms_ctl_t::rx_key
const uint rx_key
Received MC key/P2P source ID & seq code; reading this clears the received packet.
Definition
spinn_extra.h:678
system_controller_t::io_set
sc_io_t io_set
Writing a 1 sets IO register bit.
Definition
spinn_extra.h:1753
sc_misc_control_t::test
uint test
read value on Test pin
Definition
spinn_extra.h:1546
sc_clock_mux_t::mem
uint mem
clock selector for SDRAM; see sc_clock_source
Definition
spinn_extra.h:1629
router_diagnostic_filter_t::pattern_destination
uint pattern_destination
packet dest (Tx link[5:0], MP, local ¬MP, dump)
Definition
spinn_extra.h:989
router_diversion_t::L1
uint L1
Diversion rule for link 1.
Definition
spinn_extra.h:889
router_t::error::key
const uint key
error packet routing word
Definition
spinn_extra.h:935
sdram_qos_t::enable
uint enable
QoS enable.
Definition
spinn_extra.h:1278
sdram_timing_config_t::t_dqss
uint t_dqss
write to DQS time
Definition
spinn_extra.h:1230
sc_misc_control_t::jtag_tdo
uint jtag_tdo
read value on JTAG_TDO pin
Definition
spinn_extra.h:1552
router_multicast_route_t::routes::processors
uint processors
The physical processors to route to.
Definition
spinn_extra.h:1007
router_diagnostic_filter_t::emergency_routing
uint emergency_routing
Emergency Routing field = 3, 2, 1 or 0.
Definition
spinn_extra.h:977
system_controller_t::set_cpu_irq
sc_magic_proc_map_t set_cpu_irq
Writing a 1 sets a processor’s interrupt line.
Definition
spinn_extra.h:1721
router_t::dump::payload
const uint payload
dumped packet data payload
Definition
spinn_extra.h:948
dma_stats_control_t::enable
uint enable
Enable collecting DMA statistics.
Definition
spinn_extra.h:470
dma_global_control_t::crc_error_interrupt
uint crc_error_interrupt
interrupt if dma_status_t::crc_error set
Definition
spinn_extra.h:438
sdram_dll_status_t::s0
uint s0
Strobe 0 faster than Clock.
Definition
spinn_extra.h:1314
comms_rx_status_t::received
uint received
Rx packet received.
Definition
spinn_extra.h:649
sdram_dll_user_config1_t::tuning::tune_0
uint tune_0
Fine tuning control on delay line 0.
Definition
spinn_extra.h:1390
sdram_dll_user_config0_t::s2
uint s2
Input select for delay line 2 {def, alt, 0, 1}.
Definition
spinn_extra.h:1354
router_diagnostic_filter
static volatile router_diagnostic_filter_t *const router_diagnostic_filter
Router diagnostic filters.
Definition
spinn_extra.h:1075
dma_description_t::crc
uint crc
check (read) or generate (write) CRC
Definition
spinn_extra.h:340
router_error_status_t::error_count
uint error_count
16-bit saturating error count
Definition
spinn_extra.h:817
sdram_dll_user_config0_t::enable_force_inc_dec
uint enable_force_inc_dec
Enable forcing of Incing and Decing.
Definition
spinn_extra.h:1368
sdram_ram_config_t::column
uint column
number of column address bits (8-12)
Definition
spinn_extra.h:1187
dma_status_t::paused
uint paused
DMA transfer is PAUSED.
Definition
spinn_extra.h:390
sc_magic_subsystem_map_t::clock_gen
uint clock_gen
System AHB & Clock Gen (pulse reset only)
Definition
spinn_extra.h:1488
watchdog_control_t::reset_enable
uint reset_enable
Enable the Watchdog reset output (1)
Definition
spinn_extra.h:1999
comms_tx_control_t::not_full
uint not_full
Tx buffer not full, so it is safe to send a packet.
Definition
spinn_extra.h:615
sdram_timing_config_t::t_mrd
uint t_mrd
mode register command time
Definition
spinn_extra.h:1232
comms_ctl_t::tx_data
uint tx_data
32-bit data for transmission
Definition
spinn_extra.h:669
watchdog_controller_t::raw_status
const watchdog_status_t raw_status
Raw interrupt status register.
Definition
spinn_extra.h:2044
sc_magic_subsystem_map_t::system_noc
uint system_noc
System NoC.
Definition
spinn_extra.h:1480
vic_mask_t::interrupt_bits::router_error
uint router_error
Router error - packet parity, framing, or time stamp error.
Definition
spinn_extra.h:143
router_diagnostic_filter_t::enable_counter_event_interrupt
uint enable_counter_event_interrupt
enable interrupt on counter event
Definition
spinn_extra.h:995
vic_mask_t::interrupt_bits::cc_rx_ready
uint cc_rx_ready
Comms controller packet received.
Definition
spinn_extra.h:121
router_dump_outputs_t::processor
uint processor
Fascicle Processor link error caused dump.
Definition
spinn_extra.h:837
vic_mask_t::interrupt_bits::dma_done
uint dma_done
DMA controller transfer complete.
Definition
spinn_extra.h:133
sdram_dll_user_config1_t::word
uint word
Tuning control word.
Definition
spinn_extra.h:1405
dma_direction_t
dma_direction_t
DMA transfer direction, see dma_description_t::direction.
Definition
spinn_extra.h:352
DMA_DIRECTION_WRITE
@ DMA_DIRECTION_WRITE
write to system bus (SDRAM)
Definition
spinn_extra.h:356
DMA_DIRECTION_READ
@ DMA_DIRECTION_READ
read from system bus (SDRAM)
Definition
spinn_extra.h:354
system_controller_t::reset_flags
uint reset_flags
Reset flags register.
Definition
spinn_extra.h:1763
sc_clock_mux_t::rdiv
uint rdiv
divide Router clock by Rdiv+1 (= 1-4)
Definition
spinn_extra.h:1637
comms_ctl_t::rx_status
comms_rx_status_t rx_status
Indicates packet reception status.
Definition
spinn_extra.h:673
ethernet_controller_t::status
const ethernet_general_status_t status
General status.
Definition
spinn_extra.h:1926
system_controller_t::reset_code
const sc_reset_code_t reset_code
Indicates cause of last chip reset.
Definition
spinn_extra.h:1741
system_controller_t::misc_control
sc_misc_control_t misc_control
Miscellaneous control bits.
Definition
spinn_extra.h:1745
router_diagnostic_counter_ctrl_t::reset
ushort reset
write a 1 to reset diagnostic counter 15..0
Definition
spinn_extra.h:861
vic_mask_t::interrupt_bits::cc_tx_overflow
uint cc_tx_overflow
Comms controller transmit buffer overflow.
Definition
spinn_extra.h:129
ethernet_general_command_t::receive_promiscuous
uint receive_promiscuous
Receive promiscuous packets enable.
Definition
spinn_extra.h:1834
vic_mask_t::interrupt_bits::ethernet_tx
uint ethernet_tx
Ethernet transmit frame interrupt.
Definition
spinn_extra.h:147
router_control_t::reinit_wait_counters
uint reinit_wait_counters
re-initialise wait counters
Definition
spinn_extra.h:737
dma_status_t::processor_id
uint processor_id
hardwired processor ID identifies CPU on chip
Definition
spinn_extra.h:422
vic_mask_t::interrupt_bits::router_diagnostic
uint router_diagnostic
Router diagnostic counter event has occurred.
Definition
spinn_extra.h:139
sdram_cas_latency_t::cas_lat
uint cas_lat
CAS latency in memory clock cycles.
Definition
spinn_extra.h:1221
router_diagnostic_filter_t::emergency_routing_mode
uint emergency_routing_mode
Emergency Routing mode.
Definition
spinn_extra.h:979
router_p2p_table_entry_t::routes::route3
router_p2p_route route3
Third packed route.
Definition
spinn_extra.h:1043
sc_pll_control_t::freq_range
uint freq_range
frequency range (see sc_frequency_range)
Definition
spinn_extra.h:1591
vic_vector_control_t::source
uint source
interrupt source
Definition
spinn_extra.h:208
ethernet_controller_t::receive_write
const ethernet_receive_pointer_t receive_write
Receive frame buffer write pointer.
Definition
spinn_extra.h:1942
dma_description_t::transfer_id
uint transfer_id
software defined transfer ID
Definition
spinn_extra.h:348
watchdog_controller_t::value
const uint value
Current count value.
Definition
spinn_extra.h:2038
sdram_dll_status_t::s3
uint s3
Strobe 3 faster than Clock.
Definition
spinn_extra.h:1326
sdram_dll_status_t::c2
uint c2
Clock faster than strobe 2.
Definition
spinn_extra.h:1324
router_diagnostic_counter_ctrl_t::enable
ushort enable
enable diagnostic counter 15..0
Definition
spinn_extra.h:859
sc_magic_subsystem_map_t::security_code
uint security_code
SYSTEM_CONTROLLER_MAGIC_NUMBER to enable write
Definition
spinn_extra.h:1494
sc_monitor_id_t::arbitrate_request
uint arbitrate_request
Write 1 to set MP arbitration bit (see system_controller_t::monitor_arbiter)
Definition
spinn_extra.h:1526
timer_pre_divide
timer_pre_divide
Values for timer_control_t::pre_divide.
Definition
spinn_extra.h:264
TIMER_PRE_DIVIDE_16
@ TIMER_PRE_DIVIDE_16
Divide by 16.
Definition
spinn_extra.h:268
TIMER_PRE_DIVIDE_256
@ TIMER_PRE_DIVIDE_256
Divide by 256.
Definition
spinn_extra.h:270
TIMER_PRE_DIVIDE_1
@ TIMER_PRE_DIVIDE_1
Divide by 1.
Definition
spinn_extra.h:266
ethernet_controller_t::interrupt_clear
ethernet_interrupt_clear_t interrupt_clear
Interrupt clear.
Definition
spinn_extra.h:1938
ethernet_general_status_t::transmit_active
uint transmit_active
Transmit MII interface active.
Definition
spinn_extra.h:1848
vic_interrupt_handler_t
void(* vic_interrupt_handler_t)(void)
The type of an interrupt handler.
Definition
spinn_extra.h:102
dma_t::current_tcm_address
const void * current_tcm_address
Active TCM address.
Definition
spinn_extra.h:510
dma_description_t::privilege
uint privilege
DMA transfer mode is user (0) or privileged (1)
Definition
spinn_extra.h:346
ethernet_receive_pointer_t::rollover
uint rollover
Rollover bit - toggles on address wrap-around.
Definition
spinn_extra.h:1906
ethernet_phy_control_t::smi_input
uint smi_input
SMI data input.
Definition
spinn_extra.h:1876
vic_mask_t::interrupt_bits::gpio9
uint gpio9
Signal on GPIO[9].
Definition
spinn_extra.h:171
sdram_dll_user_config1_t::tuning::tune_2
uint tune_2
Fine tuning control on delay line 2.
Definition
spinn_extra.h:1394
sc_reset_code_t::reset_code
uint reset_code
One of sc_reset_codes.
Definition
spinn_extra.h:1500
router_control_t::monitor_processor
uint monitor_processor
Monitor Processor ID number.
Definition
spinn_extra.h:733
sc_io_t::gpio
uint gpio
GPIO pins.
Definition
spinn_extra.h:1577
sdram_status_t::chips
uint chips
Number of different chip selects (1, 2, 3, 4)
Definition
spinn_extra.h:1121
router_control_t::begin_emergency_wait_time
uint begin_emergency_wait_time
wait1; wait time before emergency routing
Definition
spinn_extra.h:739
router_diagnostic_filter_t::counter_event_occurred
uint counter_event_occurred
counter event has occurred (sticky)
Definition
spinn_extra.h:993
vic_mask_t::interrupt_bits::ethernet_phy
uint ethernet_phy
Ethernet PHY/external interrupt.
Definition
spinn_extra.h:151
dma_status_t::write_buffer_full
uint write_buffer_full
write buffer is full
Definition
spinn_extra.h:394
timer_interrupt_status_t::status
uint status
The flag bit.
Definition
spinn_extra.h:276
dma_description_t::burst
uint burst
burst length = 2B×Width, B = 0..4 (i.e max 16)
Definition
spinn_extra.h:342
dma_description_t::length_words
uint length_words
length of the DMA transfer, in words
Definition
spinn_extra.h:334
ethernet_receive_descriptor_pointer_t::ptr
uint ptr
Receive descriptor read pointer.
Definition
spinn_extra.h:1914
sdram_timing_config_t::t_rp
uint t_rp
precharge to RAS delay
Definition
spinn_extra.h:1242
system_controller_t::cpu_soft_reset_level
sc_magic_proc_map_t cpu_soft_reset_level
Level control of CPU resets.
Definition
spinn_extra.h:1729
vic_mask_t::interrupt_bits::watchdog
uint watchdog
Watchdog timer interrupt.
Definition
spinn_extra.h:109
dma_global_control_t::write_buffer_error_interrupt
uint write_buffer_error_interrupt
interrupt if dma_status_t::write_buffer_error set
Definition
spinn_extra.h:450
sdram_dll_user_config1_t::tuning::tune_3
uint tune_3
Fine tuning control on delay line 3.
Definition
spinn_extra.h:1396
spinnaker_packet_control_byte_t::nn::route
uchar route
Routing information.
Definition
spinn_extra.h:576
sdram_dll_status_t::c0
uint c0
Clock faster than strobe 0.
Definition
spinn_extra.h:1316
router_status_t::interrupt_active
uint interrupt_active
combined Router interrupt request
Definition
spinn_extra.h:761
sdram_status_t::status
uint status
Config, ready, paused, low-power.
Definition
spinn_extra.h:1115
timer_controller_t::interrupt_clear
uint interrupt_clear
Interrupt clear (any value may be written)
Definition
spinn_extra.h:290
comms_ctl_t
SpiNNaker communications controller registers.
Definition
spinn_extra.h:665
comms_rx_status_t
Indicates packet reception status.
Definition
spinn_extra.h:625
comms_source_addr_t
P2P source address.
Definition
spinn_extra.h:653
comms_tx_control_t
Controls packet transmission.
Definition
spinn_extra.h:607
dma_control_t
DMA control register.
Definition
spinn_extra.h:368
dma_description_t
DMA descriptor.
Definition
spinn_extra.h:330
dma_global_control_t
DMA global control register.
Definition
spinn_extra.h:426
dma_stats_control_t
DMA statistics control register.
Definition
spinn_extra.h:468
dma_status_t
DMA status register.
Definition
spinn_extra.h:386
dma_t
DMA controller registers.
Definition
spinn_extra.h:478
dma_timeout_t
DMA timeout register.
Definition
spinn_extra.h:458
ethernet_controller_t
Ethernet controller registers.
Definition
spinn_extra.h:1922
ethernet_general_command_t
Ethernet general command.
Definition
spinn_extra.h:1818
ethernet_general_status_t
Ethernet general status.
Definition
spinn_extra.h:1846
ethernet_interrupt_clear_t
Ethernet interrupt clear register.
Definition
spinn_extra.h:1890
ethernet_phy_control_t
Ethernet PHY (physical layer) control.
Definition
spinn_extra.h:1872
ethernet_receive_descriptor_pointer_t
Ethernet receive descriptor pointer.
Definition
spinn_extra.h:1912
ethernet_receive_descriptor_t
Ethernet received message descriptor.
Definition
spinn_extra.h:1954
ethernet_receive_pointer_t
Ethernet receive data pointer.
Definition
spinn_extra.h:1902
ethernet_tx_length_t
Ethernet frame transmit length.
Definition
spinn_extra.h:1858
router_control_t
Router control register.
Definition
spinn_extra.h:717
router_diagnostic_counter_ctrl_t
Router diagnostic counter enable/reset.
Definition
spinn_extra.h:857
router_diagnostic_filter_t
SpiNNaker router diagnostic filter.
Definition
spinn_extra.h:973
router_diversion_t
Router diversion rules, used to handle default-routed packets.
Definition
spinn_extra.h:885
router_dump_outputs_t
Router dump outputs.
Definition
spinn_extra.h:833
router_dump_status_t
Router dump status.
Definition
spinn_extra.h:843
router_error_status_t
Router error status.
Definition
spinn_extra.h:815
router_fixed_route_routing_t
Fixed route and nearest neighbour packet routing control.
Definition
spinn_extra.h:913
router_status_t
Router status.
Definition
spinn_extra.h:745
router_t
SpiNNaker router controller registers.
Definition
spinn_extra.h:925
router_t::dump
Packet-dump-related registers.
Definition
spinn_extra.h:942
router_t::error
Error-related registers.
Definition
spinn_extra.h:931
router_timing_counter_ctrl_t
Router timing counter controls.
Definition
spinn_extra.h:865
sc_clock_mux_t
System controller clock multiplexing control.
Definition
spinn_extra.h:1615
sc_link_disable_t
System controller link and router control.
Definition
spinn_extra.h:1693
sc_magic_proc_map_t
System controller processor select.
Definition
spinn_extra.h:1464
sc_magic_subsystem_map_t
System controller subsystem reset target select.
Definition
spinn_extra.h:1474
sc_misc_control_t
System controller miscellaneous control.
Definition
spinn_extra.h:1538
sc_monitor_id_t
System controller monitor election control.
Definition
spinn_extra.h:1520
sc_mutex_bit_t
System controller mutex/interlock.
Definition
spinn_extra.h:1685
sc_pll_control_t
System controller phase-locked-loop control.
Definition
spinn_extra.h:1581
sc_reset_code_t
System controller last reset status.
Definition
spinn_extra.h:1498
sc_sleep_status_t
System controller sleep status.
Definition
spinn_extra.h:1665
sc_temperature_t
System controller temperature status/control.
Definition
spinn_extra.h:1673
sdram_cas_latency_t
Memory CAS latency.
Definition
spinn_extra.h:1217
sdram_chip_t
Memory chip configuration.
Definition
spinn_extra.h:1288
sdram_command_t
Memory controller command.
Definition
spinn_extra.h:1131
sdram_controller_t
Memory controller registers.
Definition
spinn_extra.h:1258
sdram_direct_command_t
Memory controller direct command.
Definition
spinn_extra.h:1156
sdram_dll_status_t
Memory delay-locked-loop (DLL) test and status inputs.
Definition
spinn_extra.h:1308
sdram_dll_t
SDRAM delay-locked-loop (DLL) control registers.
Definition
spinn_extra.h:1409
sdram_dll_user_config0_t
Memory delay-locked-loop (DLL) test and control outputs.
Definition
spinn_extra.h:1348
sdram_qos_t
Memory QoS settings.
Definition
spinn_extra.h:1276
sdram_ram_config_t
Memory configuration.
Definition
spinn_extra.h:1185
sdram_refresh_t
Memory refresh period.
Definition
spinn_extra.h:1209
sdram_status_t
Memory controller status.
Definition
spinn_extra.h:1113
sdram_timing_config_t
Memory timimg configuration.
Definition
spinn_extra.h:1228
spinnaker_packet_control_byte_t::fr
Fixed-route packet only fields.
Definition
spinn_extra.h:583
spinnaker_packet_control_byte_t::mc
Multicast packet only fields.
Definition
spinn_extra.h:554
spinnaker_packet_control_byte_t::nn
Nearest-neighbour packet only fields.
Definition
spinn_extra.h:572
spinnaker_packet_control_byte_t::p2p
Peer-to-peer packet only fields.
Definition
spinn_extra.h:563
system_controller_t
System controller registers.
Definition
spinn_extra.h:1715
timer_control_t
Timer control register.
Definition
spinn_extra.h:244
timer_controller_t
Timer controller registers.
Definition
spinn_extra.h:282
timer_interrupt_status_t
Timer interrupt status flag.
Definition
spinn_extra.h:274
vic_control_t
VIC registers.
Definition
spinn_extra.h:178
vic_vector_control_t
VIC individual vector control.
Definition
spinn_extra.h:206
watchdog_control_t
Watchdog timer control register.
Definition
spinn_extra.h:1995
watchdog_controller_t
Watchdog timer control registers.
Definition
spinn_extra.h:2034
watchdog_status_t
Watchdog timer status registers.
Definition
spinn_extra.h:2005
router_multicast_route_t
SpiNNaker router multicast route.
Definition
spinn_extra.h:1001
router_p2p_table_entry_t
A packed word in the P2P routing table.
Definition
spinn_extra.h:1035
router_packet_header_t
Router error/dump header.
Definition
spinn_extra.h:777
sc_io_t
System controller general chip I/O pin access.
Definition
spinn_extra.h:1560
sdram_dll_user_config1_t
Memory delay-locked-loop (DLL) fine-tune control.
Definition
spinn_extra.h:1386
spinnaker_packet_control_byte_t
The control byte of a SpiNNaker packet.
Definition
spinn_extra.h:539
vic_mask_t
Mask describing interrupts that can be selected.
Definition
spinn_extra.h:105
watchdog_lock_t
Watchdog timer lock register.
Definition
spinn_extra.h:2013
spinnaker.h
uint64
unsigned long long uint64
WD_CODE
#define WD_CODE
uchar
unsigned char uchar
uint
unsigned int uint
NUM_CPUS
#define NUM_CPUS
ushort
unsigned short ushort
NUM_LINKS
#define NUM_LINKS
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