spinnaker_tools 3.4.0
SpiNNaker API, sark, sc&mp, bmp firmware and build tools
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spin1_api_params.h
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1
29/*
30 * Copyright (c) 2011 The University of Manchester
31 *
32 * Licensed under the Apache License, Version 2.0 (the "License");
33 * you may not use this file except in compliance with the License.
34 * You may obtain a copy of the License at
35 *
36 * https://www.apache.org/licenses/LICENSE-2.0
37 *
38 * Unless required by applicable law or agreed to in writing, software
39 * distributed under the License is distributed on an "AS IS" BASIS,
40 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41 * See the License for the specific language governing permissions and
42 * limitations under the License.
43 */
44
45#ifndef __SPINN_API_PARAM_H__
46#define __SPINN_API_PARAM_H__
47
48
49// ------------------------------------------------------------------------
50// internal constants and parameters -- not visible in the API
51// ------------------------------------------------------------------------
52// ---------------------
53/* simulation control */
54// ---------------------
55#if 0 // DKF: are these unused?
56/* synchronization barrier key and mask codes */
57#define GO_KEY (uint) ((0x1ffff << 11) | 0)
58#define RDYGO_KEY (uint) ((0x1ffff << 11) | 1)
59#define RDY1_KEY (uint) ((0x1ffff << 11) | 2)
60#define RDY2_KEY (uint) ((0x1ffff << 11) | 3)
61#define BARRIER_MASK (uint) (0xffffffff)
62
63#define BARRIER_GO_WAIT 50000
64#define BARRIER_RDY2_WAIT 25000
65#define BARRIER_RDYGO_WAIT 25000
66#define BARRIER_LOCK_WAIT 50000
67#define BARRIER_RESEND_WAIT 100
68
69#define ROUTER_INIT_WAIT 5000
70
71/* lock usage */
72#define CLEAR_LCK 0
73#define RTR_INIT_LCK 0xad
74#define RDYGO_LCK 0xbe
75#endif
76
79 EAST = 0,
80 NORTH_EAST = 1,
81 NORTH = 2,
82 WEST = 3,
83 SOUTH_WEST = 4,
84 SOUTH = 5
85};
86
88#define API_WARN TRUE
90#define API_DEBUG TRUE
92#define API_DIAGNOSTICS TRUE
94#define NON_ROOT FALSE
96#define API_PRINT_DLY 200
97
100 NO_ERROR = 0,
101 TASK_QUEUE_FULL = 1,
102 DMA_QUEUE_FULL = 2,
103 PACKET_QUEUE_FULL = 4,
104 WRITE_BUFFER_ERROR = 8,
105 SYNCHRO_ERROR = 16
106};
107// --------------------------------
108
109// ----------------
110/* data transfer */
111// ----------------
113//TODO: may need adjustment for SpiNNaker
114#define DMA_BURST_SIZE 4
116#define DMA_WIDTH 1
118#define DMA_QUEUE_SIZE 16
120#define USE_WRITE_BUFFER FALSE
121// ---------------------------
122
123// -----------------
124// communications */
125// -----------------
127#define TX_PACKET_QUEUE_SIZE 16
128// TX control register programming
130#define TX_TCR_MCDEFAULT 0x00000000
132#define TX_FULL_MASK 0x40000000
134#define TX_EMPTY_MASK 0x80000000
136#define RX_RECEIVED_MASK 0x80000000
137// -----------------
138
139// --------------
140/* user events */
141// --------------
143#define USER_EVENT_QUEUE_SIZE 4
144
145// --------------------
146/* memory allocation */
147// --------------------
149#define RTS_STACKS 4096
150// --------------------
151
152// -----------------------
153/* scheduler/dispatcher */
154// -----------------------
162// -----------------------
163
164// -----------------------
166// -----------------------
167
169 SYS_MC_ENTRIES = 1,
170 APP_MC_ENTRIES = (MC_TABLE_SIZE - SYS_MC_ENTRIES)
171};
172
173// -----------------------
175// -----------------------
189
190// ------------------------------------------------------------------------
191
192// ------------------------------------------------------------------------
193// helpful macros
194// ------------------------------------------------------------------------
199#define CHIP_ADDR(x, y) ((x << 8) | y)
203#define P2P_ROUTE(addr) (1 << p2p_get(addr))
207#define CORE_ROUTE(core) (1 << (core + NUM_LINKS))
208// ------------------------------------------------------------------------
209
210// ------------------------------------------------------------------------
211// internal pre-defined types -- not visible in the API
212// ------------------------------------------------------------------------
213// ----------------
214/* data transfer */
215// ----------------
224
233// ----------------
234
235// -----------------
236/* communications */
237// -----------------
239typedef struct {
243} packet_t;
244
253// -----------------
254
255// --------------
256/* user events */
257// --------------
259typedef struct {
263
272
273// -----------------------
274/* scheduler/dispatcher */
275// -----------------------
277typedef struct {
280} cback_t;
281
288
297
300
302#ifdef __GNUC__
303typedef void (*isr_t) (void);
304#else
305typedef __irq void (*isr_t) (void);
306#endif
307// ------------------------------------------------------------------------
308
309// ------------------------------------------------------------------------
310// internal variables -- not visible in the API
311// ------------------------------------------------------------------------
313static volatile isr_t * const vic_vectors = (isr_t *) (VIC_BASE + 0x100);
315static volatile uint * const vic_controls = (uint *) (VIC_BASE + 0x200);
316
317// ------------------------------------------------------------------------
318
319#endif /* __SPINN_API_PARAM_H__ */
@ NUM_EVENTS
Count of possible events.
Definition spin1_api.h:63
void(* callback_t)(uint, uint)
User callback for event handling.
Definition spin1_api.h:109
spin1_api_multicast_entries
Allocation of entries in MC table.
Definition spin1_api_params.h:168
spin1_api_callback_queue_params
callback queue parameters
Definition spin1_api_params.h:156
@ NUM_PRIORITIES
Number of priorities.
Definition spin1_api_params.h:159
@ TASK_QUEUE_SIZE
Size of task queue.
Definition spin1_api_params.h:160
@ N_TASK_QUEUES
Definition spin1_api_params.h:157
callback_t cback
Pointer to the function to call.
Definition spin1_api_params.h:284
uint end
Definition spin1_api_params.h:249
#define DMA_QUEUE_SIZE
internal DMA queue size
Definition spin1_api_params.h:118
uint TCR
The MC packet control word.
Definition spin1_api_params.h:242
uint arg0
The first arbitrary parameter.
Definition spin1_api_params.h:260
uint start
Index of first event.
Definition spin1_api_params.h:267
uint * tcm_address
Address in local TCM.
Definition spin1_api_params.h:221
spin1_api_error_codes
internal error/warning return codes
Definition spin1_api_params.h:99
uint arg1
The second arbitrary parameter.
Definition spin1_api_params.h:286
static volatile isr_t *const vic_vectors
VIC vector table.
Definition spin1_api_params.h:313
uint arg0
The first arbitrary parameter.
Definition spin1_api_params.h:285
static volatile uint *const vic_controls
VIC control table.
Definition spin1_api_params.h:315
spin1_api_vic_priorties
VIC priorities.
Definition spin1_api_params.h:176
@ RX_READY_PRIORITY
Multicast message ready to receive.
Definition spin1_api_params.h:181
@ CC_TMT_PRIORITY
Comms controller timeout.
Definition spin1_api_params.h:183
@ SOFT_INT_PRIORITY
Software-driven interrupt.
Definition spin1_api_params.h:184
@ DMA_DONE_PRIORITY
DMA complete.
Definition spin1_api_params.h:180
@ TIMER1_PRIORITY
Timer interrupt.
Definition spin1_api_params.h:179
@ SARK_PRIORITY
Communication with SARK/SCAMP.
Definition spin1_api_params.h:177
@ DMA_ERR_PRIORITY
DMA error.
Definition spin1_api_params.h:186
@ FR_READY_PRIORITY
Fixed route message ready to receive.
Definition spin1_api_params.h:182
@ TIMER2_PRIORITY
Timer 2 interrupt (events)
Definition spin1_api_params.h:178
uint tag
User label.
Definition spin1_api_params.h:219
spin1_api_link_orientations
link orientation codes
Definition spin1_api_params.h:78
callback_t cback
Pointer to the function to call.
Definition spin1_api_params.h:278
uint end
Definition spin1_api_params.h:293
void(* isr_t)(void)
interrupt service routine
Definition spin1_api_params.h:303
uint start
Index of first transfer.
Definition spin1_api_params.h:228
uint end
Definition spin1_api_params.h:229
uint description
Control descriptor.
Definition spin1_api_params.h:222
uint start
Index of first task.
Definition spin1_api_params.h:292
int priority
The interrupt priority.
Definition spin1_api_params.h:279
uint * system_address
Address in SDRAM (or other shared memory)
Definition spin1_api_params.h:220
cback_t callback[NUM_EVENTS]
The external interrupt handlers.
Definition spin1_api.c:113
uint end
Definition spin1_api_params.h:268
uint data
The MC packet payload (if defined)
Definition spin1_api_params.h:241
uint key
The MC packet key.
Definition spin1_api_params.h:240
uint start
Index of first packet.
Definition spin1_api_params.h:248
#define USER_EVENT_QUEUE_SIZE
internal user event queue size
Definition spin1_api_params.h:143
uint id
ID.
Definition spin1_api_params.h:218
uint arg1
The second arbitrary parameter.
Definition spin1_api_params.h:261
#define TX_PACKET_QUEUE_SIZE
Size of outbound packet queue.
Definition spin1_api_params.h:127
An external interrupt handler.
Definition spin1_api_params.h:277
Describes a DMA transfer.
Definition spin1_api_params.h:217
The queue of DMA transfers.
Definition spin1_api_params.h:227
A multicast packet.
Definition spin1_api_params.h:239
The queue of callbacks to do.
Definition spin1_api_params.h:291
An internal interrupt/callback handler.
Definition spin1_api_params.h:283
The queue of multicast packets to be sent.
Definition spin1_api_params.h:247
The type of the fixed-capacity queue of user events.
Definition spin1_api_params.h:266
Describes the parameters to pass to a user event.
Definition spin1_api_params.h:259
#define VIC_BASE
Vectored interrupt controller base address.
Definition spinnaker.h:253
unsigned int uint
Unsigned integer - 32 bits.
Definition spinnaker.h:39
#define MC_TABLE_SIZE
Multicast table size (entries)
Definition spinnaker.h:696