spinnaker_tools 3.4.0
SpiNNaker API, sark, sc&mp, bmp firmware and build tools
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Interrupt handlers for Spin1API. More...
#include <sark.h>
#include <spin1_api.h>
#include <spin1_api_params.h>
#include <scamp_spin1_sync.h>
Functions | |
void | schedule (uchar event_id, uint arg0, uint arg1) |
Wrapper for schedule_sysmode() that handles interrupts. | |
void | cc_rx_ready_isr (void) |
Handles an incoming multicast packet. | |
void | cc_rx_ready_fiqsr (void) |
Handles an incoming multicast packet. (FIQ) | |
void | cc_fr_ready_isr (void) |
Handles an incoming fixed-route packet. | |
void | cc_fr_ready_fiqsr (void) |
Handles an incoming fixed-route packet. (FIQ) | |
void | cc_rx_error_isr (void) |
Clears errors from the communications controller. | |
void | cc_tx_empty_isr (void) |
Comms controller ready to send interrupt handler. | |
void | dma_done_isr (void) |
DMA complete interrupt handler. | |
void | dma_done_fiqsr (void) |
DMA complete interrupt handler. (FIQ) | |
void | dma_error_isr (void) |
DMA error interrupt handler. | |
void | timer1_isr (void) |
Timer 1 interrupt handler. | |
void | timer1_fiqsr (void) |
Timer 1 interrupt handler. (FIQ) | |
void | soft_int_isr (void) |
Software-initiated interrupt handler. | |
void | soft_int_fiqsr (void) |
Software-initiated interrupt handler. (FIQ) | |
void | sark_int (void *pc) |
Handles messages from SCAMP. | |
void | sark_fiqsr (void) |
Variables | |
uchar | user_pending |
uint | user_arg0 |
uint | user_arg1 |
uint | ticks |
number of elapsed timer periods | |
uint | timer_tick |
timer tick period | |
uint | timer_tick_clocks |
timer tick period in clock cycles | |
int | drift |
drift in clock cycles per timer tick | |
int | drift_accum |
accumulation of drifts | |
int | drift_sign |
sign of the drift | |
int | time_to_next_drift_update |
timer ticks until drift needs to be updated | |
dma_queue_t | dma_queue |
The pending DMA transfers. | |
tx_packet_queue_t | tx_packet_queue |
The pending SpiNNaker packets to transmit. | |
user_event_queue_t | user_event_queue |
The pending user event callbacks to call. | |
Interrupt handlers for Spin1API.
Wrapper for schedule_sysmode() that handles interrupts.
[in] | event_id | ID of the event triggering a callback |
[in] | arg0 | argument to be passed to the callback |
[in] | arg1 | argument to be passed to the callback |
void cc_rx_ready_isr | ( | void | ) |
Handles an incoming multicast packet.
This interrupt service routine is called in response to receipt of a packet from the router. Chips are configured such that fascicle processors receive only multicast neural event packets. In response to receipt of a MC packet a callback is scheduled to process the corresponding routing key and data.
Checking for parity and framing errors is not performed. The VIC is configured so that the interrupts raised by erroneous packets prompt execution of cc_rx_error_isr() which clears them.
void cc_rx_ready_fiqsr | ( | void | ) |
Handles an incoming multicast packet. (FIQ)
This interrupt service routine is called in response to receipt of a packet from the router. Chips are configured such that fascicle processors receive only multicast neural event packets. In response to receipt of a MC packet a callback is scheduled to process the corresponding routing key and data.
Checking for parity and framing errors is not performed. The VIC is configured so that the interrupts raised by erroneous packets prompt execution of cc_rx_error_isr() which clears them.
void cc_fr_ready_isr | ( | void | ) |
Handles an incoming fixed-route packet.
This interrupt service routine is called in response to receipt of a packet from the router. Chips are configured such that fascicle processors receive only multicast neural event packets. In response to receipt of a MC packet a callback is scheduled to process the corresponding routing key and data.
Checking for parity and framing errors is not performed. The VIC is configured so that the interrupts raised by erroneous packets prompt execution of cc_rx_error_isr() which clears them.
void cc_fr_ready_fiqsr | ( | void | ) |
Handles an incoming fixed-route packet. (FIQ)
This interrupt service routine is called in response to receipt of a packet from the router. Chips are configured such that fascicle processors receive only multicast neural event packets. In response to receipt of a MC packet a callback is scheduled to process the corresponding routing key and data.
Checking for parity and framing errors is not performed. The VIC is configured so that the interrupts raised by erroneous packets prompt execution of cc_rx_error_isr() which clears them.
void cc_rx_error_isr | ( | void | ) |
Clears errors from the communications controller.
This interrupt service routine is called in response to receipt of a packet from the router with either parity or framing errors. The routine simply clears the error and disposes of the packet. The monitor processor may observe packet errors by reading from the router diagnostic registers.
void cc_tx_empty_isr | ( | void | ) |
Comms controller ready to send interrupt handler.
This interrupt service function is called when the comms controller transmit buffer is empty. The function dequeues packets queued for transmission by spin1_send_mc_packet() function and writes them to the comms controller hardware, until either the packet queue is empty or the comms controller is full.
This interrupt is only enabled when there is at least one message to send in the transmit queue.
void dma_done_isr | ( | void | ) |
DMA complete interrupt handler.
This interrupt service routine is called upon completion of a DMA transfer. A user callback is scheduled (with two parameters, the ID of the completed transfer and the user-provided transfer tag) and the next DMA transfer request is dequeued and fulfilled. The completion and subsequent scheduling of transfers must be atomic (as they are in this uninterruptable ISR) otherwise transfer requests may not be completed in the order they were made.
void dma_done_fiqsr | ( | void | ) |
DMA complete interrupt handler. (FIQ)
This interrupt service routine is called upon completion of a DMA transfer. A user callback is scheduled (with two parameters, the ID of the completed transfer and ‘1’ indicating transfer success) and the next DMA transfer request is dequeued and fulfilled. The completion and subsequent scheduling of transfers must be atomic (as they are in this uninterruptable ISR) otherwise transfer requests may not be completed in the order they were made.
void dma_error_isr | ( | void | ) |
DMA error interrupt handler.
This interrupt service function is called when a DMA transfer error arises. Currently, such an event causes termination of the simulation.
void timer1_isr | ( | void | ) |
Timer 1 interrupt handler.
This interrupt service routine is called upon countdown of the processor's primary timer to zero. In response, a callback is scheduled.
void timer1_fiqsr | ( | void | ) |
Timer 1 interrupt handler. (FIQ)
This interrupt service routine is called upon countdown of the processor's primary timer to zero. In response, a callback is scheduled.
void soft_int_isr | ( | void | ) |
Software-initiated interrupt handler.
This interrupt service routine is called upon receipt of software controller interrupt, triggered by a "USER EVENT".
void soft_int_fiqsr | ( | void | ) |
Software-initiated interrupt handler. (FIQ)
This interrupt service routine is called upon receipt of software controller interrupt, triggered by a "USER EVENT".
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extern |
Handles messages from SCAMP.
Interrupt handler for CPU interrupt from monitor processor. Entry and exit are via wrapper code sark_int_han() in "sark_alib.s" This handler executes in System mode with interrupts enabled.
Handles watchdog timer responses, signals, SDP message reception. Delegates to:
[in] | pc | Where the CPU was executing when the interrupt happened. Used for watchdog reporting. |
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extern |
The pending user event callbacks to call.
Registered by spin1_trigger_user_event()